Hybrid Stack Register Processor Architecture for Java Execution
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Solution Overview
Problem
Existing processors face challenges in efficiently executing both stack-based and non-stack based instruction sets in battery-operated devices like cellular phones, which require low power consumption and minimal memory usage while supporting multimedia functionality.
Innovation Solution
A processor architecture that combines a Java Stack Machine with a Main Processor Unit, enabling the execution of stack-based and register-based instructions, with a multi-entry stack and registers that store the top of the stack address and data value, allowing for efficient execution of Java bytecodes and complementary register-based operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor executes both stack-based and register-based instruction sets, then execution speed and productivity are improved, but device complexity increases
Solution Approach 1:
The patent merges a Java Stack Machine (JSM) and a Main Processor Unit (MPU) into a single hybrid processor architecture. The JSM executes stack-based Java bytecodes while the MPU handles register-based operations, and both instruction sets share common execution resources including the ALU, register file, and memory interface. This combining approach enables the processor to execute both instruction sets simultaneously without requiring separate dedicated execution paths, thereby improving productivity while controlling complexity through resource sharing.
Solution Approach 2:
The processor implements multi-functionality by providing a unified instruction set architecture that supports both stack-based Java bytecode operations and register-based operations. The same physical components (ALU, register file, memory bus) serve dual purposes: the JSM uses them for Java execution while the MPU uses them for native operations. This universality allows the processor to handle diverse workloads efficiently, from Java applications to native code, without requiring separate specialized hardware for each instruction set type.
2Adaptability or versatility
If a processor implements multimedia functionality, then adaptability and versatility are improved, but power consumption increases
Solution Approach 1:
The processor employs dynamic workload adaptation through its hybrid architecture. The control logic can dynamically switch between executing Java bytecodes via the JSM and native operations via the MPU based on the current workload requirements. For multimedia tasks, the system can selectively use register-based operations for performance-critical paths while using stack-based operations for higher-level abstractions, optimizing power consumption by activating only the necessary execution paths rather than continuously running both instruction sets at full capacity.
3Quantity of substance
If a processor uses minimal memory, then device complexity and power consumption are reduced, but execution speed may worsen
Solution Approach 1:
The patent implements a nested architecture where the JSM and MPU share common execution resources in a nested fashion. The register file, ALU, and memory interface are nested within both instruction set execution paths, allowing both to access the same physical resources without requiring duplicate memory structures. This nesting enables the processor to maintain fast execution speeds through shared high-speed resources while using minimal memory overall, as the same physical memory structures serve both Java and native execution needs rather than requiring separate dedicated memory spaces for each instruction set.
Data Source
AI summary
A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some embodiments of the invention, the processor may comprise a multi-entry stack usable in at least a stack-based instruction set, logic coupled to and managing the stack, and a plurality of registers coupled to the logic and addressable through a second instruction set that provides register-based and memory-based operations.