Hybrid Stacked Semiconductor Chips with Grounded Through-Electrodes
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Solution Overview
Problem
Current semiconductor device stacking methods fail to achieve minimal thickness and compatibility with processing equipment, limiting storage capacity and integration efficiency.
Innovation Solution
A method involving the stacking of semiconductor chips with through-electrodes, where the backside surfaces of each chip are ground to expose these electrodes, allowing for further thinning and interconnection, enabling a hybrid stacking structure with reduced thickness and improved compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional stacking methods are used to vertically stack semiconductor chips, then storage capacity is increased, but the overall thickness cannot be minimized and compatibility with processing equipment is limited
Solution Approach 1:
The semiconductor chip is divided into multiple layers including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. Each layer can be independently processed and optimized, allowing the overall structure to achieve minimal thickness while maintaining high storage capacity through the stacked configuration
Solution Approach 2:
Multiple semiconductor layers are nested vertically with each layer containing circuit patterns and electrodes. The first semiconductor layer contains first circuit patterns with first electrodes, the second layer contains second circuit patterns with second electrodes, and the third layer contains third circuit patterns with third electrodes, creating a nested structure that maximizes storage density within minimal thickness
2Quantity of substance
If conventional stacking methods are used to vertically stack semiconductor chips, then storage capacity is increased, but compatibility with processing equipment is limited
Solution Approach 1:
Different regions of the semiconductor structure have different properties optimized for specific functions. The first, second, and third semiconductor layers have locally optimized circuit patterns and electrode configurations that enable compatibility with various processing equipment while maintaining high storage capacity
Solution Approach 2:
The semiconductor layers are prepared in advance with pre-formed circuit patterns and electrodes before stacking. The first electrodes, second electrodes, and third electrodes are预先 formed on their respective layers, allowing for precise alignment and connection during the stacking process, which improves compatibility with automated processing equipment
3Length of stationary object
If backside surfaces are ground to expose through-electrodes for further thinning and interconnection, then thickness is reduced and compatibility is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming circuit patterns on separate semiconductor layers, grinding backside surfaces to expose electrodes, and stacking layers in sequence. This segmentation allows each step to be optimized independently, reducing overall manufacturing complexity despite the multiple operations required
Solution Approach 2:
The backside surfaces of the semiconductor layers are ground in advance to expose the through-electrodes before the stacking process. This preliminary action ensures that electrodes are properly exposed and positioned, facilitating easier and more accurate interconnection during stacking, which actually reduces the complexity of the subsequent assembly steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with minimized thickness, enhanced compatibility with processing equipment, and increased productivity, while also allowing for electrical inspection and repair, thus improving yield and electrical characteristics.
Implementation Method 1
The backside surface of the second semiconductor chip is ground to expose the through-electrode of the second semiconductor chip
Implementation Method 2
The first backside surface is ground so that the first semiconductor chip has a first reduced thickness
Implementation Method 3
The third backside surface is ground to reduce a thickness of the third semiconductor chip
Data Source
AI summary
A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.