Hybrid Storage Command Queue Segmentation for Latency Reduction
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Solution Overview
Problem
Existing data storage devices (DSDs) face inefficiencies in handling multiple data access commands due to differences in access times between solid state and disc memories, leading to increased latency and reduced performance.
Innovation Solution
Implementing a command queue system that separates data access commands for solid state and disc memories, allowing for pipelining and buffering of commands to optimize execution and reduce latency by prioritizing faster access times for solid state memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data access commands are handled in a single queue without separation, then device complexity is reduced, but latency increases due to slower disc memory operations blocking faster solid state memory operations
Solution Approach 1:
The patent divides the single command queue into separate queues: a first command queue for solid state memory operations and a second command queue for disc memory operations. This segmentation allows independent processing of commands for each memory type, preventing slower disc operations from blocking faster solid state operations, thereby reducing overall latency while maintaining manageable complexity through structured organization.
Solution Approach 2:
The patent introduces a new dimension to command processing by adding memory-type-specific queue separation. Instead of a single-dimensional sequential processing model, the system now operates in a multi-dimensional space where commands are routed to different queues based on target memory type, enabling parallel processing paths that reduce latency without proportionally increasing complexity.
2Productivity
If commands are processed sequentially without pipelining, then device complexity is minimized, but productivity decreases due to idle times between operations
Solution Approach 1:
The patent implements preliminary action by pre-queuing multiple commands in memory before execution. The controller loads command sequences into the first and second command queues in advance, allowing the memory devices to execute operations in a pipelined manner without waiting for each command to be individually processed by the host, thereby improving throughput while keeping the queving mechanism relatively simple.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining filled command queues for both solid state and disc memory operations. The controller continuously refills these queues with pending operations, eliminating idle periods between commands and ensuring that memory devices remain productive throughout operation, thus enhancing overall productivity without requiring complex dynamic scheduling.
Data Source
AI summary
Systems and methods are disclosed for improving performance in of storage device latency. In an embodiment, an apparatus may comprise a controller configured to receive a first data access command at a device including a nonvolatile solid state memory and a disc memory, and when the first data access command is directed to the nonvolatile solid state memory, store the first data access command to a first command queue for the nonvolatile solid state memory. In another embodiment, a method may comprise receiving, at a data storage device, a first data access command, storing the first data access command in a first command queue, determining whether the data access command is directed to a Flash memory or a disc memory, and storing the first data access command in a second command queue when the first data access command is directed to the Flash memory.