Hybrid Storage Controller Map Structure for Data Transfer Management
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Solution Overview
Problem
Hybrid data storage devices face limitations in achieving faster overall data transfer rates due to the small proportion of solid state memory, which results in significant processing overhead and additional command loading from data cleaning and pinning operations, despite the inclusion of faster solid state memory.
Innovation Solution
A hybrid data storage device with a hard disc drive (HDD) controller coupled to non-volatile rotatable storage media and a solid state drive (SSD) controller coupled to non-volatile solid state memory, utilizing a top level controller to manage data transfers by generating a map structure with logical address sequences and gaps, directing host data transfer access commands to either HDD or SSD based on the location of data sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If solid state memory is included in hybrid data storage devices, then data transfer speed is improved, but processing overhead increases due to data cleaning and pinning operations
Solution Approach 1:
The logical address space is segmented into multiple discrete sequences with gaps between them. Each sequence represents a contiguous range of logical addresses that map to physical locations in the solid state memory. This segmentation allows the system to efficiently identify and access data in the solid state memory without requiring complex scanning of the entire address space, thereby reducing processing overhead while maintaining fast data transfer rates.
Solution Approach 2:
A map structure is introduced as an intermediary data structure that stores the mapping between logical addresses and physical locations in solid state memory. This map structure acts as a mediator between the host interface and the solid state memory, enabling the controller to quickly determine whether data resides in solid state memory without direct access overhead, thus reducing processing complexity while preserving high transfer rates.
2Speed
If solid state memory proportion is increased, then data transfer rate is improved, but device cost and complexity increase
Solution Approach 1:
The logical address space is divided into multiple discrete sequences, each representing a contiguous range of addresses that map to solid state memory. This segmentation allows the system to efficiently track and manage solid state memory contents without requiring the entire address space to be continuously monitored, reducing memory management complexity while enabling faster data transfer rates through optimized solid state memory utilization.
3Reliability
If data cleaning and pinning operations are performed, then data integrity is maintained, but host I/O transfer rates are impacted
Solution Approach 1:
The system performs preliminary actions by pre-positioning data in the solid state memory at locations identified by the map structure before host access requests arrive. This preliminary organization of data allows the controller to quickly satisfy host I/O requests directly from solid state memory without requiring real-time data cleaning or pinning operations, thereby maintaining data integrity while minimizing impact on host I/O transfer rates.
Data Source
AI summary
Apparatus and method for managing data in a hybrid data storage device. In some embodiments, the hybrid data storage device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable storage media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A local memory stores a map structure which identifies logical addresses of current version data sets stored in the solid state memory. A top level controller circuit operates responsive to the map structure to direct a selected host data transfer access command to the HDD or SSD controller circuit. The map structure may be arranged as a plurality of discrete logical address sequences, where a gap is provided between each adjacent pair of the discrete logical address sequences in the map structure.