Hybrid Sub-Pixel TFT Layout for High-Resolution Low-Leakage Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices face challenges in achieving high resolution, reducing power consumption, and improving display quality by minimizing leakage currents while supporting various frame rates.
Innovation Solution
A display panel design incorporating a silicon substrate with single-crystalline semiconductor layers, metal oxide semiconductor transistors, and specific transistor configurations, including P-type and N-type transistors, to enhance integration and reduce leakage currents, along with a method of fabrication that forms these transistors on a silicon substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of sub-pixels per unit area is increased to achieve high resolution, then display resolution is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The pixel circuit is divided into two separate transistors: a first transistor with a single-crystalline semiconductor layer for the light-emitting element control, and a second transistor with a metal oxide semiconductor layer for the compensation capacitor control. This segmentation allows each transistor to be optimized independently, enabling higher integration density without increasing overall device complexity
Solution Approach 2:
Different semiconductor materials are used in different local regions: single-crystalline semiconductor for the first transistor where high current control is needed, and metal oxide semiconductor for the second transistor where low leakage current is critical. This local quality differentiation enables high resolution displays with reduced power consumption
2Measurement precision
If transistor miniaturization is implemented to increase sub-pixel density, then display resolution is improved, but leakage current increases
Solution Approach 1:
The patent changes the material parameter of the semiconductor layer from conventional single-crystalline silicon to metal oxide semiconductor for the second transistor. Metal oxide semiconductors inherently exhibit lower off-state current due to their wide bandgap, effectively reducing leakage current even in miniaturized transistors while maintaining high resolution
Solution Approach 2:
The pixel circuit employs a composite material approach by combining single-crystalline semiconductor and metal oxide semiconductor in different transistor components. This composite structure leverages the high mobility of single-crystalline material for drive transistors and the low leakage特性 of metal oxide material for storage capacitors, achieving high resolution with minimal leakage
3Use of energy by moving object
If power consumption is reduced by minimizing leakage current, then energy efficiency is improved, but display quality and frame rate flexibility deteriorate
Solution Approach 1:
The second transistor with metal oxide semiconductor forms a compensation capacitor that stores voltage information and provides feedback to maintain stable operation. This feedback mechanism enables the display to operate at various frame rates while minimizing leakage current, as the compensation capacitor compensates for charge loss and maintains pixel voltage stability across different operating conditions
4Reliability
If single-crystalline semiconductor layers are used for transistors, then transistor performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the pixel circuit into two transistors with different semiconductor materials, allowing the first transistor to use single-crystalline semiconductor for high performance while the second transistor uses metal oxide semiconductor for low leakage. This segmentation enables selective optimization without requiring all transistors to use complex single-crystalline fabrication
Solution Approach 2:
The patent changes the semiconductor material parameter from uniform single-crystalline silicon to a combination of single-crystalline and metal oxide semiconductors. This parameter change enables simpler manufacturing for the metal oxide transistor while maintaining high overall performance through the single-crystalline transistor, balancing manufacturing ease with device reliability
Data Source
AI summary
A display panel includes: a silicon substrate; a first active pattern including a single-crystalline semiconductor layer on the silicon substrate; a first gate insulating layer covering the first active pattern; a first gate electrode on the first gate insulating layer, and including at least a portion overlapping with the first active pattern; a first interlayer insulating layer on the first gate electrode; a second active pattern on the first interlayer insulating layer, and including a metal oxide semiconductor; a second gate insulating layer covering the second active pattern; a second gate electrode on the second gate insulating layer, and including at least a portion overlapping with the second active pattern; a second interlayer insulating layer covering the second gate electrode; and a source/drain electrode layer on the second interlayer insulating layer, and connected to the first and second active patterns.