Hybrid Substrate Crystal Planes for N/P MBC Gate Control
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Solution Overview
Problem
Existing semiconductor technologies face challenges in improving device performance as device sizes continue to decrease, leading to increased complexity and inefficiency in fabrication processes.
Innovation Solution
The development of semiconductor structures formed over a hybrid substrate with N-type and P-type multi-bridge-channel (MBC) transistors on regions with different crystal orientations, utilizing a (100) and (110) crystal planes, respectively, to enhance mobility and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes continue to decrease to increase functional density, then productivity and production efficiency improve, but device performance improvement becomes more challenging and fabrication complexity increases
Solution Approach 1:
The substrate is divided into first and second regions with different crystal orientations ((100) and (110) planes respectively). N-type MBC transistors are formed in the first region while P-type MBC transistors are formed in the second region. This segmentation allows each transistor type to benefit from its optimal crystal orientation without requiring separate fabrication lines, thus improving productivity while managing complexity through specialized zones.
Solution Approach 2:
Different crystal orientations are assigned to different regions of the substrate to optimize local transistor performance. The (100) plane in the first region provides optimal characteristics for N-type transistors, while the (110) plane in the second region provides optimal characteristics for P-type transistors. This local quality approach enables improved device performance in each region while maintaining a unified fabrication process.
2Productivity
If device sizes continue to decrease to increase functional density, then production costs are lowered, but device performance improvement becomes more challenging
Solution Approach 1:
The patent implements local quality by providing N-type MBC transistors in a first region with (100) crystal plane and P-type MBC transistors in a second region with (110) crystal plane. This ensures that each transistor type operates on its optimal crystal orientation, maintaining high device performance and reliability even as overall device sizes decrease and functional density increases.
Solution Approach 2:
By segmenting the substrate into specialized regions for N-type and P-type transistors, the patent enables each transistor type to achieve optimal performance characteristics. This segmentation strategy allows continued scaling while preserving device performance through region-specific crystal orientation optimization.
3Ease of manufacture
If conventional single-crystal substrates are used, then fabrication processes are simpler, but gate control is reduced and short-channel effects increase
Solution Approach 1:
The substrate functions as a composite structure with two different crystal orientations ((100) and (110) planes) integrated into a single wafer. This composite approach enables improved gate control and reduced short-channel effects through multi-bridge-channel transistor architectures while maintaining compatibility with existing fabrication processes, bridging the gap between manufacturing simplicity and device performance.
Solution Approach 2:
The substrate is segmented into regions with different crystal orientations to enable formation of MBC transistors with multiple channels. This segmentation provides superior gate control by allowing the gate to control multiple current paths simultaneously, reducing short-channel effects while maintaining fabrication process compatibility through a unified substrate structure.
Data Source
AI summary
A semiconductor structure includes N-type MBC transistors formed over a first region of a hybrid substrate and P-type MBC transistors formed over a second region of the hybrid substrate. The first region and the second region have top surfaces with different crystal orientations. Particularly, the first region for forming the N-type MBC transistors includes a top surface having a (100) crystal plane and the second region for forming P-type MBC transistors includes a top surface having a (110) crystal plane.