Hybrid SOI-Bulk Substrate Layout for RF and Digital Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits formed on bulk semiconductor substrates or SOI substrates have different performance characteristics, limiting their ability to optimize performance for diverse device types on a single die due to structural differences and defects like crystal originated particle (COP) defects.
Innovation Solution
A multi-function substrate with distinct regions, comprising both SOI and bulk regions, is developed, where the bulk regions have a surface devoid of COP defects, allowing for selective epitaxial growth and enabling diverse devices like RF and digital devices to be integrated on a single chip, with structures like polysilicon and dielectric layers optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bulk semiconductor substrates are used, then manufacturing simplicity is maintained, but device performance is limited due to structural constraints and COP defects
Solution Approach 1:
The substrate is divided into multiple distinct regions: a first region with bulk semiconductor structure and a second region with SOI structure. This segmentation allows different device types to be formed on different regions, optimizing performance for each device type while maintaining a single substrate platform.
Solution Approach 2:
Different regions of the substrate are given different local structures and properties. The first region maintains bulk structure suitable for certain devices, while the second region has SOI structure with insulating layer suitable for other devices. This local differentiation enables tailored performance characteristics in different areas of the same substrate.
2Reliability
If SOI substrates are used, then device performance is improved, but manufacturing complexity increases and COP defects occur
Solution Approach 1:
Instead of fabricating an entire SOI substrate which is complex and prone to COP defects, the SOI structure is created only in the second region where it is needed. The first region remains as simpler bulk structure, reducing overall manufacturing complexity while still providing SOI benefits in specific areas.
Solution Approach 2:
The insulating layer and SOI structure are applied locally only in the second region rather than across the entire substrate. This localized approach reduces manufacturing steps and complexity while providing the performance benefits of SOI structure only where required for optimal device performance.
3Adaptability or versatility
If a single substrate type is used, then manufacturing process is simplified, but performance optimization for diverse device types is limited
Solution Approach 1:
The substrate is segmented into multiple regions with different structures (bulk and SOI) to support different device types. This allows the single substrate to be adaptable to diverse device requirements while maintaining a manageable overall structure rather than requiring multiple separate substrates.
Solution Approach 2:
The substrate is designed with multi-functionality by incorporating both bulk and SOI regions, enabling it to support multiple types of devices with different performance requirements on a single platform. This universal substrate can accommodate both RF devices benefiting from bulk structure and digital devices benefiting from SOI structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-function substrate enhances performance by suppressing body capacitance and cross-talk in RF devices while preventing floating body effects in digital devices, improving overall chip performance and reducing fabrication defects.
Implementation Method 1
bulk regions have a surface devoid of COP defects, allowing for selective epitaxial growth
Data Source
AI summary
The present disclosure relates to an integrated chip. The integrated chip includes an epitaxial layer arranged on a semiconductor body. A trap-rich layer is arranged on the epitaxial layer, a dielectric layer is arranged on the trap-rich layer, and an active semiconductor layer is arranged on the dielectric layer. A semiconductor material is arranged on the epitaxial layer and laterally beside the active semiconductor layer. The epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.