Hybrid Substrate MBC Transistor Layout for Strain and Leakage
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Solution Overview
Problem
Conventional source/drain features in multi-bridge-channel (MBC) transistors are inadequate in maintaining compressive strain and suppressing substrate current leakage, particularly in p-type transistors, leading to suboptimal AC and DC performance.
Innovation Solution
A hybrid substrate with (100) crystal plane in NFET regions and (110) crystal plane in PFET regions is used, along with epitaxially grown source/drain features that inherit the crystal orientations, mitigating the loss of compressive strain and enhancing both AC and DC performance without sacrificing p-type transistor DC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain features are used in MBC transistors, then manufacturing is simpler, but compressive strain is lost and substrate current leakage increases
Solution Approach 1:
The patent applies local quality by using epitaxial source/drain features with specific crystal orientations ((100) for NFET, (110) for PFET) that are grown selectively in different regions. This local differentiation maintains compressive strain in p-type transistor regions while suppressing substrate current leakage, resolving the contradiction between reliability and structural complexity.
Solution Approach 2:
The patent changes the crystal orientation parameter of the source/drain features from conventional isotropic structures to anisotropic epitaxial structures with specific orientations. The (110) orientation in PFET regions specifically maintains compressive strain, while the overall epitaxial structure suppresses leakage current, thus improving reliability without excessive complexity.
2Reliability
If hybrid substrate with different crystal planes is used, then AC and DC performance is optimized, but substrate manufacturing complexity increases
Solution Approach 1:
The hybrid substrate is segmented into distinct regions with different crystal orientations: (100) orientation for NFET regions and (110) orientation for PFET regions. This segmentation allows each region to be optimized for its specific transistor type, achieving superior AC and DC performance while managing manufacturing complexity through regional specialization.
Solution Approach 2:
Different crystal plane orientations are assigned to different locations on the substrate according to the local transistor requirements. The (110) plane in PFET regions provides optimal compressive strain and carrier mobility, while the (100) plane in NFET regions provides optimal electron mobility, thus optimizing overall transistor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution optimizes both AC and DC performances of transistors in NFET and PFET regions, ensuring high mobility and reduced leakage current, thereby improving overall semiconductor device efficiency.
Implementation Method 1
The source/drain features (256P) having (110) orientation mitigate the loss of compressive strain
Implementation Method 2
epitaxially grown source/drain features that inherit the crystal orientations
Data Source
AI summary
The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include bonding a first semiconductor substrate having (110) orientation on a second semiconductor substate having (100) orientation, forming a stack over the first semiconductor substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, patterning the stack to form a fin-shape structure, the fin-shape structure comprising a channel region and a source/drain region, recessing the source/drain region to form a source/drain trench, forming a dielectric film in the source/drain trench, and epitaxially growing an epitaxial feature over the dielectric film, the epitaxial feature being in contact with the plurality of channel layers. The epitaxial feature has (110) orientation.