Hybrid Substrate Thickness Equalization After Encapsulation

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Solution Overview

Problem

Semiconductor devices often exhibit non-uniform thickness due to variations in interconnect structures and conductive pillars during manufacturing, leading to manufacturing difficulties and defects.

Innovation Solution

A method involving post-encapsulation grinding to achieve uniform thickness by compensating for thickness variations in hybrid substrates, ensuring consistent thickness across semiconductor assemblies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple interconnect layers and conductive pillars are formed during manufacturing, then electrical functionality is improved, but thickness uniformity deteriorates

Engineering Contradiction:
Improveelectrical functionalityVSAvoidthickness uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming conductive pillars before encapsulation to compensate for expected thickness variations. The pillars are strategically designed and positioned in advance to offset variations that will occur during subsequent manufacturing steps, ensuring uniform final thickness while maintaining electrical functionality.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes parameter changes by adjusting the height and positioning of conductive pillars based on measured substrate thickness variations. By changing the geometric parameters of the pillars (height, location), the system compensates for substrate non-uniformity and achieves consistent overall device thickness.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If post-encapsulation grinding is performed to achieve uniform thickness, then thickness uniformity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvethickness uniformityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent reduces manufacturing complexity by performing preliminary thickness compensation actions before encapsulation. By establishing the correct thickness profile early in the process through conductive pillar formation, the need for complex post-encapsulation grinding operations is minimized or eliminated.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If conductive pillars are formed to compensate for thickness variations, then thickness uniformity is improved, but device complexity increases

Engineering Contradiction:
Improvethickness uniformityVSAvoiddevice structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent manages device structure complexity by optimizing the parameters of conductive pillars (height, diameter, spacing, material composition). By carefully controlling these parameters, the system achieves thickness compensation with minimal additional structural complexity, maintaining electrical functionality while achieving uniform thickness.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250336788A1Semiconductor Device and Method of Forming Hybrid Substrate with Uniform Thickness
Publication Date: 2025.10.30 STATS CHIPPAC LTD
  • US20250336788A1 patent drawing
  • US20250336788A1 patent drawing
  • US20250336788A1 patent drawing

AI summary

A semiconductor device has a first hybrid substrate with a first thickness, and a second hybrid substrate with a second thickness different from the first thickness of the first hybrid substrate. An encapsulant is deposited around the first hybrid substrate and second hybrid substrate. A portion of the first hybrid substrate and a portion of the second hybrid substrate and a portion of the encapsulant can be removed after encapsulation to achieve uniform thickness for the first hybrid substate and second hybrid substrate. The first hybrid substrate has an embedded substrate, a first interconnect structure formed over a first surface of the embedded substrate, and a second interconnect structure formed over a second surface of the embedded substrate opposite the first surface of the embedded substrate. A plurality of conductive pillars is formed over the first interconnect structure. A plurality of conductive vias is formed through the embedded substrate.