Hybrid Orientation Substrate Trench Edge Defect Resolution
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Solution Overview
Problem
Current hybrid crystal orientation techniques for semiconductor devices suffer from trench-edge defects and interface defects, leading to unreliable NMOS transistors, and existing solutions do not adequately address these issues.
Innovation Solution
A method combining the amorphization/templated recrystallization (ATR) technique with strained silicon technology, involving a silicon substrate with alternating orientations, where a stress layer is applied, and a trench is formed, followed by ion implantation, solid-phase epitaxy, and annealing to create a recrystallized and strained silicon layer, which is then filled with insulating material, to enhance transistor mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the SPE process is performed after trench isolation structure is formed, then complete recrystallization of amorphized silicon is achieved, but trench-edge defects are formed at the trench corners
Solution Approach 1:
The patent applies preliminary action by performing the SPE process before filling the trench with insulating material. This allows the amorphized silicon to be completely recrystallized while the trench structure is still open, enabling the recrystallization front to reach all areas including the trench corners without being blocked by the insulating material, thus preventing trench-edge defects
2Reliability
If high-temperature annealing at 1200-1400°C is applied after SPE process, then interface defects are eliminated, but device complexity and process difficulty increase
Solution Approach 1:
The patent applies parameter changes by modifying the annealing temperature parameter from the conventional high-temperature range (1200-1400°C) to a lower temperature range (800-1100°C). This parameter change achieves the same defect elimination effect while reducing the severity of the thermal process, thereby simplifying the overall process and reducing device complexity
3Speed
If strain silicon technology is applied to enhance mobility, then device speed is improved, but additional process steps and process complexity increase
Solution Approach 1:
The patent merges the strain silicon technology with the hybrid crystal orientation technology by forming a stress layer during the same fabrication process sequence. The stress layer is created through the same ion implantation and SPE processes used for orientation conversion, thereby achieving strain-induced mobility enhancement without adding separate process steps, thus avoiding increased process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces defects and enhances the reliability of both PMOS and NMOS transistors by creating compressive or tensile strained layers, improving device speed and mobility without introducing additional strain in the recrystallized layer.
Implementation Method 1
The strained silicon technology features causing a compressive or tensile strain in a silicon layer to enhance the mobility of holes or electrons and thereby improve the device speed
Implementation Method 2
Selected portions of the silicon layer are first amorphized with ion implantation
Implementation Method 3
a solid-phase epitaxy (SPE) process is performed to convert the amorphized silicon to silicon based on the underlying substrate
Data Source
AI summary
A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.