Hybrid Supervia Structure for Low-Resistance Hyper-Scaling
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Solution Overview
Problem
The increasing spacing between metal lines in integrated circuits leads to higher coupling capacitance, which negatively impacts signal transmission and energy consumption, and existing subtractive patterning techniques struggle with accurate via alignment and resistance issues.
Innovation Solution
A semiconductor device and method that form a supervia with a damascene lower section and a subtractive upper section, using both techniques to connect non-adjacent interconnect wiring, allowing for a hyper-scaling element that reduces capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If metal lines are spaced further apart to avoid interference, then coupling capacitance between adjacent lines is reduced, but the spacing increases which negatively impacts signal transmission and energy consumption
Solution Approach 1:
The supervia is segmented into two distinct sections: a lower section formed by damascene processing and an upper section formed by subtractive etching. This segmentation allows each section to be optimized for its specific function, with the lower section providing a narrow base for precise alignment and the upper section providing a wider opening for lower resistance, thereby reducing overall energy consumption while maintaining compact spacing
Solution Approach 2:
Different sections of the supervia structure are given different properties: the lower section has a narrower width optimized for alignment with underlying features, while the upper section has a wider width optimized for reducing resistance. This local differentiation of properties allows the structure to simultaneously achieve precise positioning and low energy consumption
2Ease of manufacture
If subtractive patterning is used to form vias, then manufacturing flexibility is improved, but alignment accuracy and resistance control deteriorate
Solution Approach 1:
The invention merges two different via formation techniques into a single supervia structure. The lower section is formed using damascene processing which provides excellent alignment accuracy, while the upper section is formed using subtractive etching which provides manufacturing flexibility. The merging of these two approaches allows the structure to achieve both precise alignment and ease of manufacture
Solution Approach 2:
The supervia is divided into two sections with different formation methods: the lower section uses damascene processing for precision, and the upper section uses subtractive etching for flexibility. This segmentation allows each technique to be applied where it is most effective, resolving the contradiction between manufacturing flexibility and alignment accuracy
3Device complexity
If a uniform via structure is used throughout, then manufacturing simplicity is maintained, but the ability to optimize for both alignment and resistance is lost
Solution Approach 1:
The via structure employs local quality differentiation with a narrow lower section for alignment optimization and a wider upper section for resistance optimization. This localized variation in dimensions throughout the via structure enhances connection quality while maintaining reasonable manufacturing complexity
Solution Approach 2:
The via is segmented into two sections with different dimensional characteristics: the lower section with smaller width optimized for alignment, and the upper section with larger width optimized for reducing resistance. This segmentation improves overall connection quality while keeping the manufacturing process manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a low-resistance connection between non-adjacent interconnects, reduces energy consumption, and avoids minimum-area constraints, facilitating density scaling and efficient signal transmission.
Implementation Method 1
an upper section of a supervia formed via subtractive etching
Implementation Method 2
a lower section of the supervia formed via damascene processing
Data Source
AI summary
A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.


