Hybrid Switch Cell Layout for SoC Power Gating IR Drop Control

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Solution Overview

Problem

Existing power management techniques in system on a chip (SoC) face challenges in reducing power consumption due to leakage current and IR drops, particularly in advanced processes where metal rail resistances increase, leading to degraded device performance and increased metal congestion.

Innovation Solution

Implementing a hybrid power gating scheme with globally distributed switches, block switches, and micro switches, along with a control system to manage power distribution, including high- and low-resistance switches, and strategically placing micro switches to mitigate inrush current and reduce IR drops.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If traditional power gating with single layer of switches is used, then power consumption is reduced, but IR drops increase and device performance degrades

Engineering Contradiction:

Improvepower consumptionVSAvoiddevice performance

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The power gating switches are divided into multiple layers (first layer, second layer, third layer) with different resistance characteristics. High-resistance switches are placed in the first layer, low-resistance switches in the second layer, and high-resistance switches in the third layer, creating a segmented structure that simultaneously achieves power reduction and performance maintenance

Inventive Principle:

Principle #1Segmentation

2Loss of energy

If more switches are added to reduce leakage current, then power consumption decreases, but metal congestion increases

Engineering Contradiction:

Improveleakage currentVSAvoidmetal congestion

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

Different regions of the circuit block are assigned different switch types based on local requirements. High-resistance switches are used in regions where power reduction is critical, while low-resistance switches are used in regions where performance is critical. This local differentiation reduces overall leakage without uniformly increasing metal congestion across the entire circuit

Inventive Principle:

Principle #3Local quality

3Loss of energy

If high-resistance switches are used throughout, then power consumption is reduced, but inrush current increases

Engineering Contradiction:

Improvepower consumptionVSAvoidinrush current

Core Design Contradiction:

Loss of energyVSForce

Solution Approach 1:

The low-resistance switches in the second layer are activated before the high-resistance switches in the first and third layers during power-up. This preliminary action of establishing low-resistance paths first prevents excessive inrush current, and then the high-resistance switches are activated to achieve power reduction

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250379576A1Hybrid switch cell scheme

Publication Date: 2025.12.11 QUALCOMM INC

AI summary

A chip includes a circuit block. globally distributed switches physically located in the circuit block, and micro switches distributed between at least two of the globally distributed switches in the circuit block.