Hybrid Switch Gate Driving With Indirect Load Current Sensing
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Solution Overview
Problem
High-power converters using exclusively SiC devices are costly and inefficient in meeting overload requirements, necessitating the development of more efficient hybrid power devices that combine wide bandgap and silicon-based switching devices to achieve higher performance and lower overall costs.
Innovation Solution
An integrated circuit with a hybrid switch comprising wide bandgap semiconductor devices and silicon devices, where a control circuit generates periodic control signals with unequal duty cycles to optimize current handling across different current ranges, and a current-sensing driver circuit estimates and adjusts the on-state current using stored I-V data and temperature measurements to minimize losses and ensure safe operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If exclusively SiC devices are used in high-power converters, then power converter efficiency and power density are improved by operating at higher switching frequencies and temperatures, but semiconductor device cost significantly increases
Solution Approach 1:
The patent combines SiC devices and silicon devices in a hybrid parallel configuration within the same power converter system. This merging allows the system to leverage the high efficiency and high-frequency capabilities of SiC devices while using cost-effective silicon devices for other operating conditions, thereby reducing overall semiconductor cost while maintaining high power converter efficiency.
Solution Approach 2:
The patent applies different device types (SiC vs. silicon) to different operational contexts within the power converter. SiC devices are deployed in situations requiring high switching frequency and high temperature operation, while silicon devices handle other load conditions. This localized application of different device qualities optimizes both performance and cost.
2Reliability
If SiC devices are sized according to overload requirements (150% for 10s-60s, 200% for 10-20 cycles), then overload performance is met, but device cost increases due to oversized components
Solution Approach 1:
The patent uses a hybrid parallel configuration where SiC devices and silicon devices work together to share the overload burden. During overload conditions, both device types contribute to current handling, allowing each device to be sized for normal operation rather than peak overload, thereby reducing cost while maintaining reliability.
Solution Approach 2:
The control system dynamically adjusts the operating state of SiC and silicon devices based on real-time load conditions. During normal operation, SiC devices operate at optimal efficiency points; during overload, the control system redistributes current between SiC and silicon devices to prevent any single device from being oversized, thus reducing cost while meeting overload requirements.
3Ease of manufacture
If hybrid devices are used to reduce cost by paralleling higher and lower cost devices, then overall device cost decreases, but control complexity increases to optimize current sharing and minimize losses
Solution Approach 1:
The patent incorporates a control system with feedback mechanisms that continuously monitor the operating conditions of SiC and silicon devices. Based on this feedback, the control system dynamically adjusts gate signals to optimize current sharing between parallel devices, minimize conduction and switching losses, and maintain safe operating areas. This feedback-based control manages the complexity while achieving optimal performance.
Solution Approach 2:
The control system is designed with pre-programmed strategies and lookup tables that define optimal operating points for SiC and silicon devices under various conditions. This preliminary preparation of control parameters simplifies real-time decision-making, reducing the perceived complexity during operation while still achieving optimized current sharing and loss minimization.
Data Source
Figure 1A
Figure 1B
Figure 1C~1D
AI summary
An integrated circuit is provided with an MCU 124, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver 122 is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch 60c) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal.