Hybrid Tap Cell Layout in Multi-Stack Semiconductors
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Solution Overview
Problem
The challenge of securing a sufficient area for logic cells in highly integrated semiconductor devices while maintaining high operating speeds and operational accuracy, particularly in multi-gate 3D transistors, has not been adequately addressed.
Innovation Solution
A multi-stack semiconductor device design incorporating a hybrid tap cell with a power tap cell and a signal tap cell in one cell region, utilizing a back-side and front-side wiring layer with through structures for vertical electrical connections, and including field-effect transistors with specific source/drain and channel configurations to optimize layout and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor devices are highly integrated with multi-gate 3D transistors, then operational accuracy and operating speeds are improved, but the area available for logic cells is reduced
Solution Approach 1:
The patent implements multi-gate 3D transistors with gates surrounding active regions in a vertical stack configuration, transitioning from planar 2D transistors to three-dimensional structures. This vertical integration allows more transistors to be packed into the same footprint area, improving operational accuracy through better gate control while maintaining sufficient logic cell area by utilizing the third dimension (vertical stacking) rather than expanding horizontally.
2Speed
If semiconductor devices are highly integrated with multi-gate 3D transistors, then operating speeds are improved, but the area available for logic cells is reduced
Solution Approach 1:
The patent employs vertical stacking of transistor components including source/drain regions, gates, and channel regions in the third dimension. This 3D configuration enables faster operating speeds through improved gate control and reduced parasitic effects, while simultaneously preserving logic cell area by stacking components vertically rather than arranging them in a planar fashion.
3Productivity
If through structures are implemented for vertical electrical connections, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent divides through structures into multiple discrete components including upper vias, through electrodes, lower vias, and contact structures at different vertical levels. This segmentation allows each component to be independently formed and controlled, simplifying the manufacturing process despite the vertical complexity, while achieving high integration density through efficient use of vertical interconnection space.
Solution Approach 2:
The patent implements nested through structures where upper vias are positioned above through electrodes, which are in turn positioned above lower vias, creating a vertically nested configuration. This nesting approach maximizes the use of vertical interconnection space, achieving high integration density while organizing complex structures in a systematic, manufacturable manner.
Data Source
AI summary
Provided is a multi-stack semiconductor device including a back-side wiring layer having a first back-side line and a second back-side line each extending in a first horizontal direction, a first FET on the back-side wiring layer and including a lower source/drain region, a second FET on the first FET and including an upper source/drain region, and a hybrid tap cell having a first tap cell and a second tap cell that are adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein the first tap cell includes a first through structure electrically connected to the first back-side line, and the second tap cell comprises a second through structure extending through an upper dummy source/drain region and electrically connected to the second back-side line, where the upper dummy source/drain region is spaced apart from the upper source/drain region in the first horizontal direction.