Hybrid Poly-Silicon/Oxide TFT Driving for Low-Frequency Displays
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Solution Overview
Problem
Existing display devices face challenges in reducing power consumption, particularly when displaying still images or operating in always-on-display modes.
Innovation Solution
The display device incorporates a combination of poly-silicon thin film transistors and oxide thin film transistors, with a driving controller that provides a gate clock signal swinging between levels during writing frames and a direct current voltage during holding frames, along with an analog driving voltage during writing frames and a lower or zero voltage during holding frames to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low-frequency driving mode is used to reduce power consumption, then energy efficiency improves, but leakage current increases causing luminance degradation
Solution Approach 1:
The patent applies parameter changes by switching between two distinct voltage states for the gate clock signal: a first voltage level during writing frames and a second voltage level during holding frames. This parameter change allows the system to reduce power consumption during holding frames while maintaining sufficient voltage to prevent leakage current and preserve luminance, thereby resolving the contradiction between energy efficiency and reliability.
2Reliability
If gate clock signal continues to swing during holding frame, then pixel data is maintained accurately, but power consumption increases
Solution Approach 1:
The patent implements periodic action by alternating the gate clock signal between active swinging states during writing frames and static voltage states during holding frames. This periodic modulation of the clock signal allows the system to perform data writing operations when needed while conserving energy during data holding periods, thus resolving the contradiction between data accuracy and power consumption.
3Use of energy by moving object
If analog driving voltage is reduced to zero during holding frame, then power consumption decreases, but data retention capability deteriorates
Solution Approach 1:
The patent applies parameter changes by adjusting the analog driving voltage to a second voltage level (which may be zero or reduced) during holding frames while maintaining a first voltage level during writing frames. This voltage parameter adjustment enables significant power reduction during data holding while the gate clock signal's voltage level changes ensure data retention capability is maintained through proper transistor control.
Data Source
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AI summary
A display device includes a display panel including a pixel including a switching element of a first type and a switching element of a second type that is different from the first type, a gate driver for generating a gate signal on the basis of a gate clock signal and providing the gate signal to the display panel, a data driver for providing data voltage to the display panel, an emission controller for providing an emission controlling signal to the display panel, and a driving controller for generating control signals for controlling the gate driver, the data driver, and the emission controller. In a low-frequency driving mode, the display panel operates in a writing frame for writing data in the pixel and in a holding frame for holding the data written in the pixel, and the driving controller provides the gate driver with a gate clock signal having a direct current voltage during the holding frame.