Hybrid Time Interleaver Layout for Lower Deinterleaver Memory

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Solution Overview

Problem

Current time interleaving technologies, such as those used in DVB-NGH, lack a detailed method for generating transmission sequences, leading to inefficiencies in resource usage and memory requirements, particularly in implementing time deinterleavers.

Innovation Solution

A time interleaver and deinterleaver system that combines block and convolutional interleaving, utilizing switches and FIFO memories to efficiently rearrange cells across codewords, reducing memory usage and enabling hybrid interleaving and deinterleaving, with specific addressing schemes to optimize memory allocation and usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional time interleaving methods (block interleaving and convolutional interleaving) are used in combination, then interleaving performance is improved, but memory usage and device complexity increase

Engineering Contradiction:
Improveinterleaving performanceVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines block interleaving and convolutional interleaving into a hybrid time interleaver that achieves the benefits of both methods. The block interleaver handles spatial distribution while the convolutional interleaver provides temporal spreading, creating a unified structure that improves interleaving performance without requiring separate independent systems for each type of interleaving.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The time interleaver is divided into multiple branches, with the first branch containing a block interleaver and subsequent branches containing convolutional interleavers. This segmentation allows different interleaving strategies to be applied to different portions of the data stream, optimizing performance while managing memory requirements through distributed architecture.

Inventive Principle:
Principle #1Segmentation

2Reliability

If hybrid interleaving with multiple branches is implemented, then interleaving effectiveness is improved, but device complexity increases

Engineering Contradiction:
Improveinterleaving effectivenessVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs dynamic switching mechanisms where switches redirect data streams between different branches based on operational requirements. The system can adaptively route data through block interleaving paths or convolutional interleaving paths, providing flexibility in managing device complexity while maintaining interleaving effectiveness under varying conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The hybrid interleaver structure serves multiple functions: it performs both block-based spatial interleaving and convolutional temporal interleaving within a single unified device. This multi-functionality reduces the need for separate dedicated interleavers, thereby managing device complexity while achieving comprehensive interleaving effectiveness.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If conventional time deinterleaving is implemented, then deinterleaving function is achieved, but memory requirements and cost increase

Engineering Contradiction:
Improvedeinterleaving functionVSAvoidmemory requirements
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent applies inverse operations in the deinterleaver that mirror the interleaving process. By inverting the switching patterns and reversing the data flow through branches in opposite sequence to the interleaver, the system achieves efficient deinterleaving with reduced memory requirements, as the inverted structure allows for more compact implementation of the reversal logic.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS11876727B2Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
Publication Date: 2024.01.16 PANASONIC HOLDINGS CORP
  • US11876727B2 patent drawing
  • US11876727B2 patent drawing
  • US11876727B2 patent drawing

AI summary

A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.