Hybrid Timing Analysis for Circuit Design Pessimism Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current electronic design automation (EDA) systems for integrated circuit products face inefficiencies in timing signoff verification and correction, including repeated iterations, pessimistic timing characteristics, and excessive resource requirements, leading to increased costs, time-to-market delays, and substrate area constraints.
Innovation Solution
A system and method that utilize a hybrid graph-based and path-based timing database to guide remedial transformations of circuit designs, correlating signoff timing analysis with physical implementation data to reduce false-positive violations and optimize timing corrections, by executing graph-based and path-based analyses to generate a hybrid data store for optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated transformations and iterations are performed between timing signoff and physical implementation, then timing violations can be detected and corrected, but the process becomes highly time-consuming and resource-intensive
Solution Approach 1:
The system performs preliminary actions by executing graph-based timing analysis before physical implementation optimizations are applied. This advance timing verification identifies potential violations before they manifest during iterative corrections, reducing the need for repeated transformations and decreasing overall turn around time while maintaining detection accuracy.
2Reliability
If pessimistic timing characteristics are used in timing analysis, then false-positive violations are detected, but this leads to over-fixing and increased complexity of corrections
Solution Approach 1:
The system changes the timing analysis parameters by switching from purely pessimistic graph-based analysis to a hybrid approach that incorporates path-based analysis for critical paths. This parameter modification allows the system to maintain conservative timing verification for reliability while reducing false-positive violations that would cause unnecessary over-fixing and increased correction complexity.
3Productivity
If graph-based timing analysis is used alone, then analysis speed is improved, but timing accuracy deteriorates with highly pessimistic characteristics
Solution Approach 1:
The system merges graph-based timing analysis with path-based timing analysis to create a hybrid approach. The graph-based component maintains fast analysis speed for overall timing evaluation, while the path-based component provides enhanced accuracy for critical timing paths. This combination resolves the contradiction by achieving both productivity and measurement precision through synergistic integration of both analysis methods.
4Measurement precision
If path-based timing analysis is used alone, then timing accuracy is improved, but processing and storage requirements increase significantly
Solution Approach 1:
The system segments the timing analysis process into two distinct phases: graph-based analysis for overall timing evaluation and path-based analysis only for critical paths identified by the graph-based phase. This segmentation allows the system to achieve high timing accuracy for critical paths while avoiding the excessive processing and storage requirements of applying path-based analysis to the entire circuit design.
5Reliability
If multiple iterative corrections are performed, then timing violations are reduced, but substrate area and fabrication cost increase
Solution Approach 1:
The system implements feedback mechanisms where timing analysis results feed back into the physical implementation optimization process. By continuously monitoring timing characteristics and using this feedback to guide corrections, the system achieves timing compliance with fewer iterative corrections, thereby reducing the cumulative substrate area changes and fabrication complexity that would result from multiple rounds of corrections.
Data Source
AI summary
A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.