Hybrid Timing Analysis for Integrated Circuit Design
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Solution Overview
Problem
Current pre-layout and post-layout simulation methods in integrated circuit design, such as dynamic and static timing analysis, have limitations including reliance on default layout-dependent effects, manual work complexities, and over-pessimistic results, especially in dealing with complex clock networks and false paths.
Innovation Solution
A hybrid timing analysis method that combines the high accuracy of dynamic timing analysis with the static stage-based path traversing of static timing analysis, allowing for accurate simulation across multiple operation modes and automatic elimination of false paths, using a 3D spatial coordinate system and netlists to generate detailed timing analysis reports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic timing analysis is used for pre-layout and post-layout simulation, then measurement precision is improved, but device complexity and manual work increase
Solution Approach 1:
The patent combines static timing analysis and dynamic timing analysis into a hybrid approach. Static timing analysis is used for pre-layout simulation to establish baseline timing paths, while dynamic timing analysis is applied selectively for post-layout simulation on identified critical paths. This merging allows the system to achieve high measurement precision without requiring full dynamic analysis of the entire circuit, thereby reducing device complexity and manual intervention.
Solution Approach 2:
The patent segments the timing analysis process into distinct phases: pre-layout static timing analysis to identify timing paths, and post-layout dynamic timing analysis focused only on those identified paths. This segmentation allows the complex dynamic analysis to be applied only where necessary rather than to the entire circuit, reducing overall computational complexity and manual work while maintaining high measurement precision on critical timing paths.
2Device complexity
If static timing analysis is used, then device complexity is reduced, but measurement precision deteriorates due to over-pessimistic results
Solution Approach 1:
The patent introduces dynamic elements into the timing analysis by using dynamic timing analysis for post-layout simulation on critical paths identified during pre-layout static analysis. This allows the simulation to adapt to actual circuit behavior and switching conditions rather than assuming worst-case scenarios for all paths. The dynamic analysis adjusts timing calculations based on actual signal transitions and loading conditions, eliminating the over-pessimistic results inherent in pure static analysis while maintaining manageable device complexity through selective application.
3Measurement precision
If manual work is increased for complex clock networks, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent implements self-service through automated identification and analysis of clock networks. The hybrid timing analysis system automatically detects clock paths, determines their criticality, and applies appropriate analysis methods without requiring manual intervention. The system self-configures the analysis parameters and automatically processes complex clock networks using the combined static and dynamic approaches, eliminating the need for manual setup while maintaining high measurement precision and improving productivity.
Data Source
AI summary
A hybrid timing analysis method includes: receiving a pre-layout netlist, a post-layout netlist and a configuration file associated with an integrated circuit design; generating a first measurement script and an input stimulus waveform file according to the configuration file; performing a first dynamic timing analysis upon the pre-layout netlist by using the first measurement script and the input stimulus waveform file to generate a pre-layout simulation result; identifying at least one data path and at least one clock path according to the pre-layout simulation result; generating a second measurement script according to the at least on data path and at least one clock path; and performing a second dynamic timing analysis upon the post-layout netlist by using the second measurement script and the input stimulus waveform file to generate a first post-layout simulation result. Associated system and non-transitory computer readable medium are also provided.