Hybrid Timing Exception Verification for IC Design
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Solution Overview
Problem
Current methods for verifying timing exceptions in integrated circuit design are prone to human errors due to increasing complexity, with manual reviews being inefficient and automated static formal verification generating high numbers of false errors, leading to 'tool noise' and inefficiencies in design validation.
Innovation Solution
A hybrid timing exception verification approach combining static and dynamic verification methods, where static verification identifies and corrects false-path exceptions and multi-cycle paths, while dynamic verification leverages a user-supplied test-bench to detect and validate timing exceptions, significantly reducing false errors and improving design reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual review of design constraints is performed, then timing exceptions can be verified, but human errors increase with design complexity
Solution Approach 1:
The verification process is segmented into two distinct phases: static formal verification to identify potential timing exceptions, and dynamic simulation verification to validate them. This segmentation allows each phase to focus on specific aspects, reducing the cognitive load and error rate associated with manual review of complex designs.
Solution Approach 2:
A hybrid verification system acts as an intermediary between manual review and automated verification. It uses static analysis to pre-process and filter constraints, then guides dynamic simulation to verify only relevant exceptions, reducing the overall complexity burden on human reviewers.
2Productivity
If automated static formal verification is used, then manual review effort is reduced, but false error rate increases significantly
Solution Approach 1:
Static formal verification is performed as a preliminary action before dynamic simulation. It identifies potential timing exceptions that need verification, filtering out obvious cases and focusing the subsequent dynamic verification on relevant exceptions only. This preliminary filtering reduces the workload for dynamic verification while maintaining high accuracy.
Solution Approach 2:
The system implements feedback between static and dynamic verification phases. Results from static analysis inform the setup of dynamic verification, and results from dynamic verification validate and refine the static analysis findings. This feedback loop reduces false errors by cross-validating results through multiple verification approaches.
3Extent of automation
If purely functional verification is performed, then automation is achieved, but timing nature of exceptions is ignored causing false violations
Solution Approach 1:
The verification approach transitions from static functional analysis to dynamic timing-aware simulation. Static verification handles the functional aspects automatically, while dynamic simulation incorporates actual timing information and signal behavior. This dynamic approach maintains automation while correctly accounting for the timing nature of exceptions, eliminating false violations.
Data Source
AI summary
Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.