Hybrid Timing Recovery With Coarse-Fine Phase Alignment
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Solution Overview
Problem
Existing systems face challenges in synchronizing the phase of clock signals and digitized samples effectively, particularly in systems that require precise timing recovery, as they often suffer from limitations in phase step size and latency, leading to inefficiencies in hybrid timing recovery processes.
Innovation Solution
The implementation of a hybrid timing recovery approach that combines clock-controlled timing recovery and interpolated timing recovery, where a timing control circuit generates phase interpolator and digital interpolator control signals to phase shift a clock signal and digitally interpolate samples, allowing for adaptive phase adjustments based on a phase control value, thereby compensating for latency and maximizing signal folding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single timing recovery method (either clock-controlled or interpolated) is used, then the system structure is simple, but the phase adjustment flexibility and timing precision are limited
Solution Approach 1:
The patent combines clock-controlled timing recovery and interpolated timing recovery into a unified hybrid timing recovery system. The phase-locked loop (PLL) provides coarse phase adjustment while the digital interpolator provides fine phase adjustment, merging two different timing recovery approaches to achieve both broad coverage and high precision without requiring separate independent systems.
Solution Approach 2:
The timing recovery function is segmented into two distinct components: a PLL-based clock-controlled phase interpolator for coarse adjustment and a digital interpolator for fine adjustment. This segmentation allows each component to specialize in a specific adjustment range, with the PLL handling larger phase deviations and the digital interpolator handling precise fine-tuning, thereby improving overall timing precision.
2Speed
If the phase step size is increased to speed up timing recovery, then the convergence speed improves, but the timing accuracy deteriorates
Solution Approach 1:
The system dynamically adjusts the phase step size based on the current timing error magnitude. When the timing error is large, a larger phase step size is used to accelerate convergence. As the timing error decreases and the system approaches the optimal phase point, the phase step size is automatically reduced to enable precise final adjustment, thus achieving both fast convergence and high accuracy.
Solution Approach 2:
The PLL provides an initial excessive phase adjustment that may overshoot the optimal point but quickly reduces the large timing error. The digital interpolator then performs a partial fine-adjustment to precisely reach the optimal phase. This two-stage approach uses partial actions at different precision levels to achieve both speed and accuracy.
3Measurement precision
If the phase step size is decreased to improve timing accuracy, then the timing precision improves, but the convergence speed deteriorates
Solution Approach 1:
The system dynamically adjusts the phase step size based on the current timing error magnitude. When the timing error is large, a larger phase step size is used to accelerate convergence. As the timing error decreases and the system approaches the optimal phase point, the phase step size is automatically reduced to enable precise final adjustment, thus achieving both fast convergence and high accuracy.
4Loss of time
If latency is reduced to improve real-time performance, then the real-time capability improves, but the phase adjustment stability deteriorates
Solution Approach 1:
The timing recovery function is segmented into two distinct components: a PLL-based clock-controlled phase interpolator for coarse adjustment and a digital interpolator for fine adjustment. This segmentation allows each component to specialize in a specific adjustment range, with the PLL handling larger phase deviations and the digital interpolator handling precise fine-tuning, thereby improving overall timing precision.
Data Source
AI summary
An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.