Hybrid SRAM STT-MRAM TLB for GPU Memory Management
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Solution Overview
Problem
Current memory management systems, particularly in GPUs, face challenges in increasing throughput and storage capacity while reducing power consumption due to limitations in translation lookaside buffers (TLBs) implemented as static random access memory (SRAM), which have low density and are volatile, and spin-transfer torque magnetic random access memory (STT-MRAM), which has high write times.
Innovation Solution
A hybrid memory management system that combines a first TLB implemented as SRAM for rapid access and a second TLB implemented as STT-MRAM for high-density storage, where the SRAM stores page table entries and the STT-MRAM stores frequently accessed 'hot' pages, allowing simultaneous search and translation of virtual memory addresses into physical addresses, with the SRAM handling updates to minimize write time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If TLB is implemented as SRAM for rapid access, then access speed is improved, but storage capacity and power efficiency deteriorate
Solution Approach 1:
The TLB is divided into two separate structures: first TLB using SRAM for fast access to frequently used page table entries, and second TLB using STT-MRAM for storing less frequently accessed entries. This segmentation allows each memory type to operate in its optimal performance zone, resolving the contradiction between speed and storage capacity.
Solution Approach 2:
Different memory technologies are assigned to different functional zones within the TLB system. SRAM is used locally for hot pages requiring rapid access, while STT-MRAM is used for cold pages requiring high-density storage. This local quality differentiation optimizes both speed and storage capacity in their respective domains.
2Productivity
If TLB size is increased to improve page hit rate, then throughput is improved, but area and power consumption increase
Solution Approach 1:
The system changes the physical parameters of the memory technology used in TLB from traditional SRAM to hybrid SRAM-STT-MRAM configuration. STT-MRAM provides higher density with lower power consumption per bit, enabling larger TLB capacity without proportional increase in power consumption, thus improving throughput while controlling energy usage.
3Quantity of substance
If STT-MRAM is used for high-density storage, then storage capacity is improved, but write time increases
Solution Approach 1:
The TLB is segmented into first TLB (SRAM) and second TLB (STT-MRAM) with distinct access patterns. SRAM handles frequent writes to hot pages due to its fast write speed, while STT-MRAM stores cold pages where slower write time is acceptable. This segmentation resolves the write time penalty of STT-MRAM by limiting its usage to appropriate workloads.
Data Source
AI summary
Provided are a GPU and a method of managing a memory address thereby. TLBs are configured using an SRAM and an STT-MRAM so that a storage capacity is significantly improved compared to a case where a TLB is configured using an SRAM. Accordingly, the page hit rate of a TLB can be increased, thereby improving the throughput of a device. Furthermore, after a PTE is first written in the SRAM, a PTE having high frequency of use is selected and moved to the STT-MRAM. Accordingly, an increase in TLB update time which may occur due to the use of the STT-MRAM having a low write speed can be prevented. Furthermore, a read time and read energy consumption can be reduced.