Hybrid TLB with Non-Volatile Memory for Power-Cycle Data Retention
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Solution Overview
Problem
The existing memory systems face inefficiencies due to the volatility of translation lookaside buffers (TLBs), which require reinitialization upon power restoration, leading to increased TLB misses and reduced processing performance.
Innovation Solution
Incorporating a non-volatile memory as a secondary cache to store address conversion information from the TLB during power off, allowing for rapid restoration and reducing TLB misses upon power return.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a TLB is formed by SRAM, then access speed is improved, but data is erased when power is turned off requiring reinitialization
Solution Approach 1:
The patent merges SRAM and non-volatile memory into a hybrid TLB structure. The SRAM portion provides high-speed access for frequently used address conversion information, while the non-volatile memory portion preserves data across power cycles. This combination allows the TLB to maintain both fast access and data persistence without requiring complete reinitialization after power restoration.
2Reliability
If TLB is reinitialized upon power restoration, then data persistence is ensured, but processing performance is reduced due to increased TLB misses
Solution Approach 1:
The non-volatile memory portion performs preliminary action by preserving address conversion information before power is turned off. This preliminary data retention eliminates the need for complete reinitialization after power restoration, thereby maintaining processing performance while ensuring data persistence across power cycles.
3Reliability
If high-capacity cache memory is provided, then cache hit rate is improved, but memory utilization efficiency is reduced
Solution Approach 1:
The patent implements dynamic allocation of cache memory regions based on access patterns and power state. The cache memory is divided into regions that can be dynamically activated or deactivated, allowing the system to optimize between cache hit rate and memory utilization efficiency depending on current operational conditions rather than relying on a fixed high-capacity structure.
Data Source
AI summary
A memory system has a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory, a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address, and a first control circuitry that stores the address conversion information stored in the first translation lookaside buffer in the non-volatile memory during a power off.