Control Circuitry Hybrid TLBI-DSB Synchronization for Lower Latency
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Solution Overview
Problem
Existing data processing systems face high latency due to the need for separate execution of TLBI and DSB instructions, which are necessary for maintaining memory coherence but introduce additional latency, particularly in microprocessor architectures like Arm Limited's A-class ISA.
Innovation Solution
Implementing a hybrid TLBI+DSB operation that combines the execution of both instructions into a single DVMOp+Sync message, reducing the need for separate handshaking and response collection, thereby minimizing latency by amortizing the cost of DSB over multiple TLBI operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TLBI and DSB instructions are executed separately to maintain memory coherence, then reliability is improved, but latency increases
Solution Approach 1:
The patent combines TLBI (Translation Lookaside Buffer Invalidation) and DSB (Data Synchronization Barrier) instructions into a single hybrid operation. The control circuitry receives a unified request that performs both TLB invalidation and synchronization barrier functions atomically, eliminating the need for separate execution of these two instructions. This merging reduces the total number of handshaking cycles and response collections required, directly reducing latency while maintaining the reliability benefits of both operations.
2Manufacturing precision
If separate handshaking is performed for TLBI and DSB operations, then control precision is improved, but device complexity increases
Solution Approach 1:
The control circuitry is designed to handle combined TLBI+DSB requests as a single atomic operation. Instead of implementing separate handshaking protocols for TLBI and DSB, the system uses one unified handshaking mechanism that manages both functions simultaneously. This reduces control complexity while maintaining the precision required for proper memory coherence management.
Solution Approach 2:
The control circuitry is enhanced to provide multi-functional capability, handling both TLBI and DSB operations through a single request interface. The control circuitry can operate in multiple modes: processing separate TLBI and DSB requests independently, or processing them as a combined hybrid operation. This universality allows the system to adapt to different operational requirements while simplifying the overall control structure.
3Reliability
If multiple separate instructions are used for memory coherence, then reliability is improved, but productivity decreases
Solution Approach 1:
By merging TLBI and DSB into a single hybrid instruction, the system reduces the total number of operations required for memory coherence management. The processing element can issue one request instead of two separate instructions, and the control circuitry processes this single request to accomplish both TLB invalidation and synchronization. This directly improves productivity by reducing instruction overhead and improving operation efficiency while maintaining the reliability benefits of proper memory coherence management.
Data Source
AI summary
Apparatus comprises a plurality of processing elements; and control circuitry to communicate with the plurality of processing elements by a data communication path; the control circuitry being configured, in response to a request issued by a given processing element of the plurality of processing elements, to initiate a hybrid operation by issuing a command defining the hybrid operation to a group of processing elements comprising at least a subset of the plurality of processing elements, the hybrid operation comprising performance of a control function selected from a predetermined set of one or more control functions and initiation of performance of a synchronization event, the synchronization event comprising each of the group of processing elements providing confirmation that any control functions pending at that processing element have reached at least a predetermined stage of execution; in which the given processing element is configured to inhibit the issuance of any further requests to the control circuitry until each of the group of processing elements has provided such confirmation.