Transceiver Loopback Testing With Hybrid Scan Registers
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Solution Overview
Problem
Scannable flip-flop registers used for testing digital circuitry consume more area, power, and are slower than non-scannable flip-flop registers, while non-scannable registers lack high fault coverage and visibility during testing.
Innovation Solution
Implementing scannable flip-flop registers for low-frequency digital circuits and non-scannable flip-flop registers for high-frequency circuits, allowing testing at normal operation frequencies with high fault coverage and visibility, using a hybrid approach in transceiver circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scannable flip-flop registers are used for testing digital circuitry, then high fault coverage and visibility during testing are achieved, but area consumption, power consumption, and speed are degraded
Solution Approach 1:
The patent applies local quality by making only specific register circuits scannable (those requiring high fault coverage) while keeping other register circuits non-scannable. This selective approach ensures that scannable registers are used only where testing visibility is critical, thereby achieving high fault coverage for essential circuits while minimizing the overall area and power consumption associated with scannable register implementation.
2Reliability
If scannable flip-flop registers are used for testing digital circuitry, then high fault coverage and visibility during testing are achieved, but power consumption increases
Solution Approach 1:
The patent applies local quality by making only specific register circuits scannable (those requiring high fault coverage) while keeping other register circuits non-scannable. This selective approach ensures that scannable registers are used only where testing visibility is critical, thereby achieving high fault coverage for essential circuits while minimizing the overall area and power consumption associated with scannable register implementation.
3Reliability
If scannable flip-flop registers are used for testing digital circuitry, then high fault coverage and visibility during testing are achieved, but testing speed decreases
Solution Approach 1:
The patent applies local quality by making only specific register circuits scannable (those requiring high fault coverage) while keeping other register circuits non-scannable. This selective approach ensures that scannable registers are used only where testing visibility is critical, thereby achieving high fault coverage for essential circuits while minimizing the overall area and power consumption associated with scannable register implementation.
4Productivity
If non-scannable flip-flop registers are used for high-frequency circuits, then area, power, and speed are optimized, but fault coverage and testing visibility are reduced
Solution Approach 1:
The patent applies local quality by making only specific register circuits scannable (those requiring high fault coverage) while keeping other register circuits non-scannable. This selective approach ensures that scannable registers are used only where testing visibility is critical, thereby achieving high fault coverage for essential circuits while minimizing the overall area and power consumption associated with scannable register implementation.
Solution Approach 2:
The patent segments the register circuits into two distinct groups: scannable registers for circuits requiring high fault coverage and non-scannable registers for high-frequency circuits where area and power are critical. This segmentation allows each type of register to be optimally applied to its intended purpose, resolving the contradiction between testing quality and resource efficiency.
Data Source
AI summary
A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.