Hybrid Power Transistor Gate Timing to Suppress Switching Ringing
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Solution Overview
Problem
High voltage applications with low output voltage requirements face issues such as parasitic inductance and capacitor formation leading to significant voltage overshoots and under-damped ringing on the switching node, causing EMI and potential damage to power switches, while traditional solutions increase system cost and complexity.
Innovation Solution
A hybrid power transistor apparatus with parallel-connected transistor cells and controlled gate drive signals is used to attenuate ringing by introducing delays and overlaps in the switching process of high-side and low-side switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fast turn-on of the high-side switch is used, then the system responds quickly, but parasitic inductance and capacitor form a high Q LC circuit generating significant voltage overshoots and under-damped ringing on the switching node
Solution Approach 1:
The patent divides the high-side switch into two separate switches (first high-side switch and second high-side switch) that operate at different times. The first high-side switch turns on quickly to establish the conductive channel, while the second high-side switch is turned on with a delay to provide damping resistance and reduce ringing. This segmentation allows the system to achieve both fast response and reduced oscillations.
Solution Approach 2:
The patent applies preliminary action by turning on the second high-side switch with a controlled delay after the first high-side switch. This delayed activation prepares the damping resistance in advance to suppress the LC oscillation that would otherwise occur during the fast turn-on of the primary switching path, thereby preventing ringing before it fully develops.
2Object-generated harmful factors
If the slew rate of the switching node voltage is reduced to resolve voltage spikes, then voltage spikes are mitigated, but switching losses increase significantly
Solution Approach 1:
The patent applies local quality by introducing damping resistance only during the specific transition period when voltage spikes occur. The second high-side switch is turned on with a delay and remains active only long enough to suppress the LC oscillation and mitigate voltage spikes. After this brief period, the second switch is turned off, allowing the primary switching path to operate with minimal resistance and thus minimizing switching losses during the main conduction period.
3Object-generated harmful factors
If a longer blanking time is used in the current detector circuit to handle ringing, then ringing is accommodated, but the current detection accuracy deteriorates when the turn-on pulse is very narrow
Solution Approach 1:
The patent converts the harmful ringing effect into a beneficial controlled oscillation by using the second high-side switch to deliberately introduce damping resistance. This controlled damping reduces the amplitude and duration of the ringing, allowing the current detector circuit to use a shorter blanking time while still accurately detecting the current during the narrow turn-on pulse of the first high-side switch.
4Reliability
If higher voltage rating MOSFETs are used to overcome voltage spikes, then voltage spike damage is prevented, but system cost increases
Solution Approach 1:
The patent changes the operating parameters of standard-voltage MOSFETs by controlling their switching时序 (timing sequence). By turning on the second high-side switch with a specific delay after the first high-side switch, the patent dynamically adjusts the effective damping resistance during the critical voltage spike period. This allows the use of lower voltage-rated, cheaper MOSFETs while still preventing voltage spike damage through controlled parameter manipulation rather than relying on higher voltage ratings.
Data Source
AI summary
A hybrid power transistor apparatus includes a first switching element comprising a first number of transistor cells connected in parallel between a first terminal and a second terminal of the apparatus, wherein gates of the first number of transistor cells are connected together, and the gates of the first number of transistor cells are connected to an output of a first gate drive circuit, and a second switching element comprising a second number of transistor cells connected in parallel between the first terminal and the second terminal of the apparatus, wherein gates of the second number of transistor cells are connected together, and the gates of the second number of transistor cells are connected to an output of a second gate drive circuit, and wherein a delay is placed between the output of the first gate drive circuit and the output of the second gate drive circuit.