Hybrid Transistor Power Gating Switch for Leakage Control
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Solution Overview
Problem
In 45 nm technology, core logic transistors experience excessive gate and gate-induced drain leakage, making them unsuitable as switches, while using input/output transistors as switches results in area increase and performance degradation.
Innovation Solution
A hybrid switch transistor is developed with dielectric thickness similar to IO transistors and incorporating logic transistor extension and halo implants, allowing for reduced gate length and operation between cut-off and linear modes, thereby minimizing leakage and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If core logic transistors are used as switches, then transistor performance is maintained, but gate and GIDL leakage exceeds acceptable budget
Solution Approach 1:
The switch transistor is divided into multiple functional segments: a header transistor with thick oxide for leakage control, a footer transistor for performance, and intermediate structures. This segmentation allows each part to optimize for its specific function while collectively solving the leakage-performance contradiction.
Solution Approach 2:
The switch uses a composite transistor structure combining different transistor types (header and footer transistors with different oxide thicknesses) into a single functional unit. This composite approach enables simultaneous achievement of low leakage (from thick oxide header) and high performance (from optimized footer).
2Object-generated harmful factors
If IO transistors are used as switches, then gate and GIDL leakage is reduced, but area increases and performance degrades
Solution Approach 1:
Different regions of the switch structure have different oxide thicknesses optimized for their local functions: thick oxide in the header transistor region for leakage control, and thinner oxide in the footer transistor region for performance. This local differentiation reduces overall area while maintaining low leakage.
Solution Approach 2:
The invention changes the oxide thickness parameter selectively across different parts of the switch structure. By using thick oxide only where needed for leakage control (header) and thinner oxide where performance is critical (footer), the overall area is reduced compared to using uniformly thick oxide IO transistors.
3Object-generated harmful factors
If IO transistors are used as switches, then gate and GIDL leakage is reduced, but transistor performance decreases
Solution Approach 1:
The switch is segmented into header and footer transistors with different oxide thicknesses. The header transistor uses thick oxide for leakage control, while the footer transistor uses optimized thickness for performance, achieving both low leakage and high performance simultaneously.
Solution Approach 2:
The composite transistor structure combines header and footer transistors with different oxide characteristics into a unified switch. This composite design leverages the leakage-resistant property of thick oxide and the performance advantage of optimized oxide thickness, achieving both goals together.
Data Source
AI summary
A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.