Hybrid Power Transistor Gate Timing for Ringing Suppression
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Solution Overview
Problem
The issue of switching node ringing and associated electromagnetic interference (EMI) in power conversion systems, particularly in high voltage applications, leads to inefficiencies and potential damage due to voltage spikes, necessitating a control method to reduce these issues.
Innovation Solution
A hybrid power transistor apparatus with parallel-connected transistor cells and controlled gate drive signals, incorporating delays between the gate drive circuits for high-side and low-side switches, to attenuate ringing and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a fast turn-on of the high-side switch is used to reduce switching losses, then switching efficiency is improved, but voltage overshoots and under-damped ringing are generated on the switching node
Solution Approach 1:
The high-side switch is divided into two separate switches (first high-side switch and second high-side switch) that operate at different times. The first high-side switch turns on quickly to minimize switching losses, while the second high-side switch turns on with a delay to suppress voltage overshoots and ringing, effectively segmenting the switching function to resolve the contradiction between efficiency and voltage stability
Solution Approach 2:
The second high-side switch is configured to turn on before the high-side switching node voltage reaches its maximum level, preliminarily establishing a conductive path that prevents voltage overshoots and under-damped ringing from occurring in the first place, thereby maintaining both efficiency and voltage stability
2Reliability
If the slew rate of the switching node voltage is reduced to resolve voltage spikes, then voltage spike damage is prevented, but switching losses increase
Solution Approach 1:
The high-side switch is segmented into two switches with different turn-on characteristics. The first switch enables fast turn-on for efficiency, while the second switch provides controlled voltage rise to prevent spikes, resolving the contradiction between reliability and energy loss through functional division
Solution Approach 2:
The patent changes the timing parameter (turn-on time) of the second high-side switch relative to the first switch, creating a controlled delay that prevents voltage spikes without significantly increasing switching losses, thus maintaining both reliability and efficiency
3Object-generated harmful factors
If a longer blanking time is used in the current detector circuit to handle ringing, then EMI issues are reduced, but the current detection accuracy deteriorates when the turn-on pulse is narrow
Solution Approach 1:
By segmenting the high-side switch into two switches, the ringing is suppressed at its source, eliminating the need for long blanking times in the current detector circuit and thereby maintaining both EMI reduction and current detection accuracy simultaneously
Solution Approach 2:
The patent converts the potential harmful effect of the second switch's delayed turn-on into a benefit by using it to suppress ringing and reduce EMI, while the narrow turn-on pulse of the first switch remains intact for accurate current detection, transforming what could be a detection challenge into an EMI solution
Data Source
AI summary
A hybrid power transistor apparatus includes a first switching element comprising a first number of transistor cells connected in parallel between a first terminal and a second terminal of the apparatus, wherein gates of the first number of transistor cells are connected together, and the gates of the first number of transistor cells are connected to an output of a first gate drive circuit, and a second switching element comprising a second number of transistor cells connected in parallel between the first terminal and the second terminal of the apparatus, wherein gates of the second number of transistor cells are connected together, and the gates of the second number of transistor cells are connected to an output of a second gate drive circuit, and wherein a delay is placed between the output of the first gate drive circuit and the output of the second gate drive circuit.


