Hybrid Through-Silicon-Via Interposer for Power Delivery
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Solution Overview
Problem
Conventional semiconductor packages face challenges with reduced current carrying capability due to miniaturized through-silicon-vias (TSVs), leading to reliability risks and decreased computing performance, as well as increased power consumption and form factor, exacerbated by power supply noise jitter and Vmin/IR drop degradations from passive devices being far apart from stacked integrated circuit devices.
Innovation Solution
The solution involves a semiconductor package design with a hybrid interposer featuring through-silicon-vias of different diameters and heights, including a recess to accommodate passive devices, which reduces parasitic impedance and enhances power delivery network integrity by using larger diameter TSVs and bumps for improved current capacity and power transmission, thereby mitigating DC and AC losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If TSV geometries are scaled down to reduce real estate space, then area is reduced, but current carrying capability deteriorates
Solution Approach 1:
The patent applies local quality by using different TSV diameters for different functions: smaller TSVs (e.g., 10-20 micrometers) for signal transmission where current carrying capability is less critical, and larger TSVs (e.g., 30-50 micrometers) for power delivery where high current capacity is required. This spatial differentiation of TSV geometries allows the interposer to simultaneously minimize area while maintaining adequate current carrying capability for power TSVs.
2Area of stationary object
If passive devices are disposed far apart from stacked integrated circuit devices, then area is reduced, but power supply noise jitter and Vmin/IR drop performance deteriorate
Solution Approach 1:
The patent transitions from planar placement to three-dimensional vertical stacking by positioning passive devices in recesses of the interposer at different vertical levels. This allows passive devices to be placed closer to stacked integrated circuit devices in the vertical dimension while maintaining acceptable area utilization. The recess structure enables passive devices to be embedded within the interposer thickness, creating short power loops that reduce noise jitter and Vmin/IR drop without increasing footprint area.
3Reliability
If TSV counts are increased to meet required current density, then current carrying capability is improved, but device complexity and form factor increase
Solution Approach 1:
The patent changes the diameter parameter of TSVs to optimize current carrying capability. By using larger diameter TSVs (30-50 micrometers) for power delivery instead of increasing the number of smaller TSVs, the patent achieves the required current density with fewer interconnect structures. This parameter change reduces device complexity while maintaining adequate current carrying capability for power transmission.
Data Source
AI summary
According to various examples, a device is described. The device may include an interposer. The device may also include a plurality of first through-silicon-vias disposed in the interposer, wherein the plurality of first through-silicon-vias have a first diameter. The device may also include a plurality of second through-silicon-vias disposed in the interposer, wherein the plurality of second through-silicon-vias have a second diameter larger than the first via diameter. The device may also include a first recess in the interposer positioned at bottom ends of the plurality of second through-silicon-vias.