Hybrid Verification Framework for IC Design Protocol
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Solution Overview
Problem
The chip design process, particularly the RTL verification phase, is time-consuming, leading to delays in completing chip design projects, and there is a need for improved methods to enhance timeliness, correctness, and completeness across different phases of chip design.
Innovation Solution
A hybrid verification framework (HVF) that uses extended state transition tables and templates to integrate verification across all phases of the design flow, enabling early formal verification of architectural entities and tracing and resolving bugs across phases, thereby reducing time-to-market and increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RTL design verification is performed traditionally, then correctness can be ensured, but the verification process becomes the most time-consuming phase
Solution Approach 1:
The patent applies preliminary action by performing formal verification of architectural entities before RTL implementation. The verification framework checks protocol correctness at the architectural level using extended state transition tables and templates, allowing bugs to be identified and resolved before the time-consuming RTL verification phase begins. This shifts verification activities to earlier design stages, reducing overall verification time while maintaining correctness.
2Productivity
If multiple chip design projects are worked on simultaneously by different groups, then throughput increases, but coordination and knowledge sharing become complex
Solution Approach 1:
The verification framework provides universal templates and extended state transition tables that can be applied across multiple chip design projects. These standardized verification artifacts allow different groups working on parallel projects to use common verification methodologies, facilitating knowledge sharing and reducing coordination complexity while maintaining high throughput.
Solution Approach 2:
The framework implements feedback mechanisms that enable automatic propagation of verification results and protocol changes across projects. When verification issues are identified in one project, the feedback system can propagate these findings to related projects, allowing coordinated resolution of issues across multiple simultaneous design efforts without increasing operational complexity.
3Adaptability or versatility
If protocol changes are incorporated rapidly, then adaptability improves, but verification completeness may be compromised
Solution Approach 1:
The verification framework enables continuous verification through automated checking of protocol changes against extended state transition tables. As protocol changes are made, the verification system continuously checks for completeness and correctness, ensuring that verification remains an ongoing process rather than a discrete phase. This allows rapid protocol iteration while maintaining verification completeness through continuous automated validation.
Data Source
AI summary
A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended state table-based specifications and the templates in all phases in the design flow, resulting in a tight revision loop of debug, verification, and validation across the phases of the design flow.