Hybrid Verification IP for Software-Hardware Co-Design
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Solution Overview
Problem
The design of hardware and software is a lengthy and complicated process, with software engineers lacking access to physical hardware during early development stages, leading to late-stage lab debugging and costly changes, especially in critical systems like flight software, where rigorous testing is essential for safety.
Innovation Solution
Incorporating software engineers into the hardware engineering team early in development and using testing frameworks that simulate real-world conditions, allowing both teams to detect issues early and implement changes efficiently, with the use of Universal Verification Methodology (UVM) and SystemVerilog for hybrid VIP development.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If hardware is simulated using physical layer protocols during early development, then software engineers can begin design without physical hardware, but software engineers face difficulty understanding hardware verification tools and physical layer protocols
Solution Approach 1:
The patent introduces an intermediary translation layer that converts physical layer protocols into network-level protocols familiar to software engineers. This intermediary allows software engineers to interact with simulated hardware using their native protocol understanding, eliminating the need to learn hardware-specific physical layer protocols while maintaining accurate hardware simulation.
Solution Approach 2:
The patent creates a virtual copy of the hardware interface that replicates the behavior of physical hardware but presents it through software-friendly network protocols. This virtual copy allows software engineers to develop and test software against hardware simulations without directly encountering hardware verification tools or physical layer protocols.
2Reliability
If hardware changes are made after boards are manufactured, then final hardware functionality can be achieved, but changes become expensive and time consuming requiring tooling modifications
Solution Approach 1:
The patent implements preliminary hardware verification through detailed hardware simulations that model the actual hardware behavior before manufacturing. By performing comprehensive verification activities in the simulation environment, potential design flaws and functionality issues are identified and corrected before physical boards are manufactured, eliminating the need for costly post-manufacturing changes.
Solution Approach 2:
The patent creates a protective layer of virtual verification that cushions against the risks of hardware manufacturing errors. By thoroughly testing hardware designs in simulation with realistic workloads and verification protocols, the system prepares for manufacturing by ensuring design correctness, thereby preventing expensive rework after production begins.
3Measurement precision
If software engineers engage in lab debugging late in the development cycle, then software can be tested with actual hardware, but visibility into circuits is limited and debugging becomes less effective
Solution Approach 1:
The patent performs preliminary software debugging and testing in the simulation environment before hardware is available. Software engineers can debug their code against simulated hardware with full circuit visibility, identifying and fixing issues early in the development cycle rather than waiting for physical hardware to become available for lab debugging.
Solution Approach 2:
The patent adds a temporal dimension to the debugging process by enabling software testing and debugging activities to occur in the time dimension before hardware availability. Through simulation, software engineers gain early debugging capability with full circuit visibility, effectively moving debugging activities to an earlier time dimension without sacrificing visibility into hardware circuits.
4Reliability
If physical layer inputs are designed to methodically stimulate hardware components, then hardware verification can be performed, but inputs fail to simulate real-world software or functions realistically
Solution Approach 1:
The patent merges hardware verification capabilities with realistic software simulation by integrating network-level protocol stacks that emulate actual software behavior. The simulation combines methodical hardware stimulation with realistic software workloads, allowing verification of both hardware functionality and software-hardware interaction under realistic conditions.
Solution Approach 2:
The patent creates a universal simulation platform that serves multiple functions: it performs traditional hardware verification through methodical stimulation while simultaneously emulating realistic software behavior and network protocols. This multi-functional simulation environment can test both hardware correctness and software-hardware compatibility with a single integrated system.
Data Source
AI summary
A system and method of verifying hardware that includes software configured to control its operation, the method comprising providing an abstracted version of hardware to be tested; verifying the functionality of the hardware; writing test bench software using physical-layer routines; drafting hybrid verification intellectual property modules, wherein the hybrid verification intellectual property modules comprise both synthesizable and non-synthesizable code and are configured to stimulate the abstracted hardware and to test software anticipated to be used in connection therewith; and creating network-level routines that can be passed to physical-layer routines as part of a hardware verification process.