Hybrid Virtual Memory Bypass Circuit for Latency Reduction

Solution Overview

Problem

Modern computer systems experience significant memory access latency due to the indirection involved in translating virtual addresses to physical addresses through page tables and translation lookaside buffers, which can delay memory access speeds, especially in data-intensive applications.

Innovation Solution

A hybrid virtual memory system that allows for both conventional page table translation and high-speed offset-based translation, where a subset of virtual addresses can bypass the page table and translation lookaside buffer, using a dedicated bypass circuit with base and limit registers to determine the memory access mode, enabling direct access to physical memory with an offset value.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If virtual address translation through page table and TLB is used, then memory address translation accuracy and process isolation are improved, but memory access latency increases

Engineering Contradiction:

Improveaddress translation accuracyVSAvoidmemory access latency

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The virtual address space is segmented into two distinct regions: a first region that uses conventional page table/TLB translation and a second region that uses direct physical address mapping. This segmentation allows the system to maintain accurate address translation for processes while providing fast direct access for specific memory regions, thereby resolving the contradiction between translation accuracy and access speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A memory management unit (MMU) acts as an intermediary that receives virtual addresses and determines whether to route them through the page table/TLB path or the direct mapping path. The MMU uses base and limit registers to identify addresses in the second region and automatically performs the appropriate translation method, eliminating the need for software intervention and reducing access latency while maintaining translation accuracy.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If direct physical address access is used, then memory access speed is improved, but address translation security and process isolation are worsened

Engineering Contradiction:

Improvememory access speedVSAvoidprocess isolation

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The virtual address space is segmented into two distinct regions: a first region that uses conventional page table/TLB translation and a second region that uses direct physical address mapping. This segmentation allows the system to maintain accurate address translation for processes while providing fast direct access for specific memory regions, thereby resolving the contradiction between translation accuracy and access speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different translation methods are applied to different regions of the virtual address space. The first region maintains conventional translation with full security checks, while the second region uses direct mapping for speed. The base and limit registers define the boundaries of these regions, ensuring that direct access is only used where appropriate and process isolation is maintained where required.

Inventive Principle:

Principle #3Local quality

3Adaptability or versatility

If hybrid memory access mode is implemented, then memory access flexibility is improved, but system complexity increases

Engineering Contradiction:

Improvememory access flexibilityVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A memory management unit (MMU) acts as an intermediary that receives virtual addresses and determines whether to route them through the page table/TLB path or the direct mapping path. The MMU uses base and limit registers to identify addresses in the second region and automatically performs the appropriate translation method, eliminating the need for software intervention and reducing access latency while maintaining translation accuracy.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs automatic mode selection for memory access without requiring software intervention. The base and limit registers are configured to define the second region, and the MMU automatically determines whether to use direct mapping or conventional translation based on the virtual address being accessed. This self-service mechanism reduces system complexity by eliminating the need for complex software management of the hybrid access mode.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS9158704B2Virtual memory management system with reduced latency

Publication Date: 2015.10.13 WISCONSIN ALUMNI RES FOUND

AI summary

A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses.