Hybrid Wafer Bonding Layout for Void-Free 3DIC Stacking
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in achieving high bonding strength and accurate bonding between stacked semiconductor wafers in 3DICs, particularly due to void generation and thermal expansion mismatches.
Innovation Solution
A method involving hybrid-bonding of semiconductor wafers with strategically designed dielectric and metallization structures, where the top surface of the first metallization structure is lower than the dielectric layer by a first distance, and the top surface of the second metallization structure is higher than its dielectric layer by a second distance, allowing for thermal expansion to fill a gap and ensure tight bonding without voids, utilizing an annealing process to achieve accurate and strong bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional hybrid-bonding is used without gap compensation, then bonding process is simple, but voids form between metallization structures due to thermal expansion mismatch
Solution Approach 1:
The patent applies preliminary action by pre-forming gaps in the dielectric layers before bonding. Specifically, a first gap is formed in the first dielectric layer and a second gap is formed in the second dielectric layer, positioned to align during bonding. These pre-formed gaps accommodate thermal expansion differences between stacked wafers, preventing void formation between metallization structures while maintaining bonding strength and precision.
2Ease of manufacture
If metallization structures are made coplanar with dielectric surfaces, then fabrication is easier, but thermal expansion causes voids during bonding
Solution Approach 1:
The patent applies local quality by creating non-uniform gap distributions in the dielectric layers. Instead of making all metallization structures coplanar with the dielectric surface, the invention forms specific gaps at strategic locations where thermal expansion will occur. This localized gap formation accommodates thermal expansion differences while maintaining ease of manufacture through targeted gap formation rather than complete coplanarity.
3Device complexity
If stacked wafers are bonded without gap compensation, then process complexity is low, but voids form reducing integration density
Solution Approach 1:
The patent applies preliminary action by pre-forming gaps in the dielectric layers before the bonding process. These gaps are strategically positioned to align during wafer stacking and accommodate thermal expansion that occurs during bonding. This approach maintains relatively low process complexity while preventing void formation, thereby preserving high integration density in the final 3DIC structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high bonding strength between semiconductor wafers with vertically located dielectric-to-dielectric and metal-to-metal bonds at different levels, ensuring accurate and void-free bonding, thereby enhancing integration density and performance in 3DICs.
Implementation Method 1
performing an annealing process such that the first top metallization structure and the second top metallization structure undergo a thermal expansion to fill the gap
Data Source
AI summary
A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.