Hybrid Wear Leveling for Memory Sub-Systems

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Solution Overview

Problem

Conventional memory sub-systems face challenges in maintaining data consistency due to race conditions and high latency caused by wear leveling operations, especially in systems with a large number of data units, leading to premature failure of memory components.

Innovation Solution

Implementing hybrid wear leveling using a hierarchy of data units with intra-SMU and inter-SMU wear leveling techniques, along with a mapping data structure and state machine to track data movement and manage wear evenly across components, ensuring data consistency and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If wear leveling operations are performed in conventional memory sub-systems, then memory component lifespan is extended, but data consistency is compromised due to race conditions and high latency

Engineering Contradiction:
Improvememory component lifespanVSAvoiddata consistency
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The patent segments wear leveling operations into two distinct types: intra-SMU wear leveling for data units within the same super management unit, and inter-SMU wear leveling for data units across different super management units. This segmentation allows different wear leveling strategies to be applied based on the specific scenario, improving both data consistency and operational efficiency while extending memory component lifespan

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a state machine as an intermediary component that tracks and manages wear leveling operations. The state machine maintains state information for each data unit, including whether wear leveling is in progress, completed, or pending. This intermediary mechanism prevents race conditions by coordinating access to mapping structures and ensuring data consistency during wear leveling operations

Inventive Principle:
Principle #24Intermediary (Mediator)

2Duration of action of stationary object

If wear leveling operations are performed in conventional memory sub-systems, then memory component lifespan is extended, but system latency increases

Engineering Contradiction:
Improvememory component lifespanVSAvoidsystem latency
Core Design Contradiction:
Duration of action of stationary objectVSLoss of time

Solution Approach 1:

By dividing wear leveling into intra-SMU and inter-SMU operations, the patent enables more efficient execution of common cases (intra-SMU) while handling less frequent cases (inter-SMU) with appropriate complexity. This segmentation reduces average latency while still providing comprehensive wear leveling coverage

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies wear leveling selectively based on wear thresholds and operational context rather than uniformly across all data units. Intra-SMU wear leveling is applied when sufficient free data units exist within the same SMU, avoiding the overhead of inter-SMU operations and reducing overall system latency

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If hybrid wear leveling with state machine is implemented, then data consistency is maintained, but device complexity increases

Engineering Contradiction:
Improvedata consistencyVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The state machine operates autonomously to track wear leveling states and coordinate operations without requiring complex external control logic. Each data unit's state is self-contained in the state machine, allowing automatic decision-making about when and how to perform wear leveling while maintaining data consistency

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The state machine maintains separate state information for intra-SMU and inter-SMU wear leveling operations, allowing independent management of each wear leveling type. This segmentation simplifies the overall control logic by handling different scenarios through dedicated state tracking mechanisms

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11874769B2Maintaining data consistency in a memory sub-system that uses hybrid wear leveling operations
Publication Date: 2024.01.16 MICRON TECHNOLOGY INC
  • US11874769B2 patent drawing
  • US11874769B2 patent drawing
  • US11874769B2 patent drawing

AI summary

A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units. Data located in data management units subsequent to the second indicator remain located in data management units of the source group of data management units and have not been copied to the destination group of data management units.