Hydrogen Barrier Local Interconnection for Memory Cell Integration
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Solution Overview
Problem
The increase in the number of memory cells in semiconductor memory devices leads to wiring delay issues due to the growth of capacitance connected to global interconnections, and the use of metal oxide ferroelectrics or high dielectrics is hindered by reduction reactions with hydrogen, which deteriorates their ferroelectric or high dielectric properties, making it difficult to miniaturize memory cells and increase integration density.
Innovation Solution
A semiconductor memory device structure featuring hydrogen non-permeable local interconnection layers that connect memory capacitors, preventing hydrogen diffusion and maintaining the integrity of the metal oxide ferroelectric or high dielectric properties, while also reducing wiring delay by minimizing the length of local interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to increase storage capacity, then storage capacity is improved, but wiring delay increases due to increased capacitance connected to global interconnections
Solution Approach 1:
The patent divides the interconnection system into global interconnections and local interconnections. Local interconnections connect capacitors within the same local region, while global interconnections connect different local regions. This segmentation reduces the capacitance burden on global interconnections, thereby reducing wiring delay while allowing increased number of memory cells.
Solution Approach 2:
The patent introduces a two-dimensional matrix array structure for organizing memory cells, with word lines and bit lines forming a grid. This spatial organization allows efficient routing of local and global interconnections, reducing wiring delay by optimizing the physical layout and connection paths.
2Quantity of substance
If metal oxide ferroelectrics or high dielectrics are used as capacitor dielectric to achieve high capacitance, then capacitance is improved, but ferroelectric or high dielectric properties deteriorate due to reduction reactions with hydrogen
Solution Approach 1:
The patent introduces a hydrogen barrier film as an intermediary layer between the metal oxide ferroelectric/high dielectric capacitor dielectric and the surrounding environment. This barrier film prevents hydrogen from reaching and reducing the dielectric material, thereby preserving its ferroelectric or high dielectric properties while allowing the use of these materials for high capacitance applications.
Solution Approach 2:
The patent creates a protective copy or barrier structure (hydrogen barrier film) that replicates the protective function needed for the dielectric material. This barrier film serves as a substitute protective layer that prevents harmful hydrogen interaction, allowing the dielectric to maintain its properties without direct exposure to reducing environments.
3Loss of time
If local interconnection is used to connect capacitors within local region, then wiring delay is reduced, but hydrogen can penetrate through interconnection layer and contact dielectric causing reduction reactions
Solution Approach 1:
The patent employs a composite interconnection structure consisting of multiple layers with different functions: a conductive layer for electrical connection and a hydrogen barrier layer for preventing hydrogen penetration. This composite structure maintains the electrical conductivity needed for low wiring delay while adding hydrogen protection to prevent reduction reactions with the dielectric material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents the deterioration of ferroelectric or high dielectric properties and reduces wiring delay, enabling higher integration density and faster operation of semiconductor memory devices by isolating memory capacitors from hydrogen and optimizing interconnection lengths.
Implementation Method 1
a first local interconnection layer that has electrical conductivity and non-permeability to hydrogen
Implementation Method 2
metal oxide ferroelectrics or metal oxide high dielectrics are used as a capacitor dielectric
Data Source
AI summary
A memory cell structure comprises a first memory capacitor that is arranged in a first local area, and includes a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper electrode; a second memory capacitor that is spaced apart from the first memory capacitor and arranged in the first local area, and includes a second lower electrode, a second upper electrode, and a second dielectric oxide film interposed between the second lower electrode and the second upper electrode; and a first local interconnection layer.