Hydrogen Treatment for Gate Dielectric Interface Quality

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Solution Overview

Problem

Advanced integrated circuits, particularly P-channel transistors, face performance reduction due to stress-related shifts in threshold voltage over time, primarily caused by charge traps at the interface between the gate dielectric and the channel region, which is exacerbated by the reduction in gate dielectric thickness and device dimensions.

Innovation Solution

A heat treatment in a hydrogen-containing ambient is applied to an exposed silicon-containing semiconductor surface before forming the gate dielectric material, enhancing the surface and near-surface crystallinity and reducing the number of charge traps, thereby improving the quality of the gate dielectric and minimizing threshold voltage degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the gate dielectric thickness is reduced to improve switching speed and drive current capability, then the operating speed increases, but charge traps are created at the interface between the gate dielectric and channel region, causing threshold voltage shifts and performance degradation

Engineering Contradiction:
Improveoperating speedVSAvoidthreshold voltage stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies a preliminary hydrogen plasma treatment to the silicon surface before depositing the gate dielectric layer. This preliminary action passivates surface states and reduces interface traps, preventing charge trap formation that would otherwise occur when using ultra-thin gate dielectrics. The treatment is performed in advance to ensure stable threshold voltage throughout device operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the physical and chemical parameters of the silicon surface through hydrogen plasma exposure, modifying surface energy, bonding configuration, and interface quality. These parameter changes reduce the density of interface states and prevent charge trap formation, enabling the use of thinner gate dielectrics without sacrificing reliability.

Inventive Principle:
Principle #35Parameter changes

2Power

If the gate dielectric thickness is reduced to increase capacitive coupling, then the drive current capability improves, but charge trap creation increases, leading to threshold voltage shifts under stress conditions

Engineering Contradiction:
Improvedrive current capabilityVSAvoidcharge trap creation
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

The hydrogen plasma treatment is applied in advance to the silicon surface before gate dielectric deposition. This preliminary action passivates surface states and creates a more stable interface, reducing the harmful charge trap creation that would otherwise occur with thin gate dielectrics under electrical stress.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the potentially harmful effect of using ultra-thin gate dielectrics (which create charge traps) into a benefit by applying hydrogen plasma treatment. This treatment transforms the interface quality, turning what would be a harmful charge trap source into a stable, low-trap interface that enables thin dielectric usage without reliability penalties.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Productivity

If advanced scaling is performed to increase circuit density, then productivity increases, but interface quality deteriorates, causing increased charge trap formation and performance variability

Engineering Contradiction:
Improvecircuit densityVSAvoidinterface quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The hydrogen plasma treatment is applied as a preliminary step before gate dielectric deposition in the scaled manufacturing process. This preliminary action ensures high interface quality even as device dimensions are reduced, preventing charge trap formation that would otherwise increase with advanced scaling.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies parameter changes through hydrogen plasma exposure, modifying surface energy, bonding configuration, and interface chemistry. These changes maintain consistent interface quality across different scaling nodes, enabling high circuit density without sacrificing manufacturing precision or interface stability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the creation of charge traps and improves the stability of the threshold voltage over the device's lifetime, offering increased design flexibility and reduced performance variability under stress conditions, particularly for P-channel transistors.

Implementation Method 1

performing at least one heat treatment in a hydrogen-containing ambient on a substrate having formed thereon an exposed silicon-containing semiconductor layer

Methodology Applied
Scientific EffectHeat treatment: Heat Treatment

Implementation Method 2

performing at least one heat treatment in a hydrogen-containing ambient on a substrate having formed thereon an exposed silicon-containing semiconductor layer

Methodology Applied
Scientific EffectHydrogenation: Hydrogenation

Data Source

PatentUS8119461B2Reducing the creation of charge traps at gate dielectrics in MOS transistors by performing a hydrogen treatment
Publication Date: 2012.02.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8119461B2 patent drawing
  • US8119461B2 patent drawing
  • US8119461B2 patent drawing

AI summary

By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.