Hyper-abrupt Junction Superlattice for Mobility and Diffusion Control

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Solution Overview

Problem

Current semiconductor devices face limitations in achieving enhanced charge carrier mobility and performance due to issues such as alloy scattering and diffusion between thin layers, which affect device mobility and reliability.

Innovation Solution

The implementation of a hyper-abrupt junction region with a superlattice structure, comprising stacked groups of semiconductor and non-semiconductor monolayers, which reduces effective mass and enhances conductivity, while also acting as a barrier to prevent dopant and material diffusion, thereby improving charge carrier mobility and device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If thin layers are used to enhance device performance, then device mobility is improved, but diffusion between layers occurs causing reliability degradation

Engineering Contradiction:
Improvedevice mobilityVSAvoidlayer stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces a superlattice structure consisting of multiple alternating monolayers of different semiconductor materials (e.g., SiGe and Si) between the thin semiconductor layers. This segmentation creates a barrier effect that prevents dopant and material diffusion while maintaining the thin-layer configuration needed for high mobility. The superlattice acts as a diffusion barrier without requiring thicker layers, thus resolving the contradiction between achieving high device mobility and preventing layer diffusion.

Inventive Principle:
Principle #1Segmentation

2Speed

If alloy scattering is reduced to enhance mobility, then charge carrier mobility is improved, but device complexity increases

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidstructure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent employs a composite superlattice structure made of alternating monolayers of different semiconductor materials (such as SiGe and Si) with controlled thicknesses. This composite structure reduces alloy scattering effects that limit charge carrier mobility while maintaining a relatively simple fabrication process using existing epitaxial growth techniques. The superlattice composite provides the mobility enhancement needed without requiring fundamentally new device architectures, thus balancing performance improvement with manufacturing feasibility.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The superlattice structure achieves higher charge carrier mobility by reducing effective mass and scattering effects, leading to improved device performance and enhanced mobility in semiconductor devices, including FETs and varactors, with potential benefits for opto-electronic applications.

Implementation Method 1

The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions

Methodology Applied
Scientific EffectQuantum confinement: Potential Well

Implementation Method 2

The superlattice structure achieves higher charge carrier mobility by reducing effective mass and scattering effects, leading to improved device performance and enhanced mobility in semiconductor devices

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20210020748A1Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
Publication Date: 2021.01.21 ATOMERA INC
  • US20210020748A1 patent drawing
  • US20210020748A1 patent drawing
  • US20210020748A1 patent drawing

AI summary

A method for making semiconductor device may include forming a hyper-abrupt junction region on a substrate and including a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The first, second, and the superlattice layers may be U-shaped. The method may further include forming a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.