Hyper-abrupt Junction Superlattice for Mobility and Diffusion Control

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Solution Overview

Problem

Current semiconductor devices face limitations in achieving enhanced charge carrier mobility and performance due to issues such as alloy scattering and diffusion between thin layers, which affect device mobility and efficiency.

Innovation Solution

The development of a hyper-abrupt junction semiconductor device incorporating a superlattice structure with stacked groups of semiconductor and non-semiconductor monolayers, where the non-semiconductor monolayers are constrained within the crystal lattice of adjacent semiconductor portions, reducing effective mass and enhancing mobility, and acting as a barrier to diffusion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If thin semiconductor layers are used to reduce alloy scattering and enhance mobility, then charge carrier mobility is improved, but diffusion between layers increases causing performance degradation

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidlayer composition stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

A non-semiconductor monolayer (intermediary layer) is inserted between adjacent semiconductor layers in the superlattice structure. This intermediary layer acts as a diffusion barrier that prevents intermixing and compositional degradation between thin semiconductor layers, while allowing the thin layer structure to be maintained for high charge carrier mobility. The intermediary layer resolves the contradiction by enabling thin layer construction without suffering from diffusion-induced composition instability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If superlattice structure with multiple monolayers is formed to reduce alloy scattering, then charge carrier mobility is enhanced, but device complexity increases

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidsuperlattice structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The superlattice structure is segmented into repeating units of semiconductor monolayers separated by non-semiconductor monolayers. This segmentation creates a modular architecture where each unit cell (semiconductor layer + non-semiconductor layer) can be replicated to form the complete superlattice. The segmented structure reduces complexity by providing a simple repeating pattern rather than requiring complex varying thicknesses or compositions, while still achieving the mobility enhancement through reduced alloy scattering in the thin semiconductor layers.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in higher charge carrier mobility, reduced ionized impurity scattering, and improved device performance by lowering conductivity effective mass and blocking dopant diffusion, thereby enhancing the conductive properties and reducing unwanted scattering effects.

Implementation Method 1

acting as a barrier to diffusion

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

reducing effective mass and enhancing mobility

Methodology Applied
Scientific EffectEffective mass reduction:

Data Source

PatentUS10937868B2Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
Publication Date: 2021.03.02 ATOMERA INC
  • US10937868B2 patent drawing
  • US10937868B2 patent drawing
  • US10937868B2 patent drawing

AI summary

A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.