Hyper-Σ Epitaxial Stressors for Channel Strain Targeting
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Solution Overview
Problem
The complexity and difficulty in controlling stress distribution in epitaxial structures for semiconductor devices, which hinders efficient improvement of carrier mobility and device performance, as existing methods struggle to effectively target the channel region with strain stress.
Innovation Solution
A method involving a substrate with gate structures, spacers, and hyper-Σ shaped epitaxial stressors formed through a series of etching processes and ion implantation, where the stressors have multiple tips pointed towards the channel region, ensuring effective stress distribution with a vertical distance of less than 450 Å, enhancing stress application to the channel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth method is used to form epitaxial structures, then carrier mobility in channel region is improved through strain stress, but fabrication complexity and process control difficulty increase
Solution Approach 1:
The patent divides the epitaxial growth process into multiple selective growth stages with different conditions. The first epitaxial layer is grown under specific conditions to provide initial strain, while the second epitaxial layer is grown under different conditions to enhance and distribute stress more effectively to the channel region, thereby improving carrier mobility while maintaining process control
Solution Approach 2:
The patent implements selective epitaxial growth that creates different epitaxial structures at different locations. The stress distribution is optimized by growing epitaxial layers with specific crystal orientations and compositions in regions adjacent to the channel, ensuring that strain stress is concentrated where needed to improve carrier mobility without requiring complex global process changes
2Speed
If epitaxial structures are formed to provide strain stress to channel region, then device speed is increased, but stress distribution control and direct targeting of channel region becomes difficult
Solution Approach 1:
The patent utilizes the crystallographic orientation dimension by growing epitaxial layers with specific orientations (e.g., <110> orientation) that naturally direct strain stress toward the channel region. This dimensional approach to stress control allows effective stress targeting without requiring complex lateral positioning, improving both device speed and stress distribution control
Solution Approach 2:
The patent employs composite epitaxial structures consisting of multiple layers with different compositions and stress characteristics. By combining layers with tensile strain and compressive strain, the patent achieves balanced and controlled stress distribution that directly targets the channel region, enhancing device speed while improving manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly improves semiconductor device performance by providing much higher stress to the channel region, effectively improving carrier mobility and device speed.
Implementation Method 1
a strain stress is generated to the channel region of the meta-oxide semiconductor (hereinafter abbreviated as MOS) transistor device
Implementation Method 2
Because the lattice constant of the epitaxial structures is larger than that of the silicon substrate, a strain stress is generated
Implementation Method 3
followed by performing an ion implantation to the first recesses
Data Source
AI summary
A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.