Hyper-Threading Processor Power-On BIOS Cache Copy Method
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Solution Overview
Problem
Conventional power-on methods for computer systems are not adaptable for processors supporting Hyper-Threading technologies, leading to a deadlock due to the 'No-Fill Cache' mode of the cache memory, which prevents the second logic unit from being initialized until the main memory is initialized, causing operational inefficiencies.
Innovation Solution
A power-on method that initializes the processor in Hyper-Threading disabled mode, copies BIOS codes to cache memory, initializes the main memory, and then re-initializes in Hyper-Threading enabled mode, using pin A31 to control the Hyper-Threading mode switch, allowing both logic units to activate and enabling full system operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the processor is initialized in Hyper-Threading disabled mode with the cache memory in No-Fill Cache mode, then the first logic unit can be activated, but the second logic unit cannot be initialized causing a deadlock
Solution Approach 1:
The patent applies preliminary action by initializing the processor in Hyper-Threading disabled mode before enabling Hyper-Threading. This preliminary initialization ensures that the cache memory is properly set up and the first logic unit is fully operational before the second logic unit is activated, preventing the deadlock condition.
Solution Approach 2:
The patent uses dynamics by making the Hyper-Threading mode switchable between disabled and enabled states through pin A31 control. This dynamic reconfiguration allows the system to transition from a stable single-logic-unit initialization state to a full dual-logic-unit operational state, resolving the contradiction between ease of initialization and full operational capability.
2Productivity
If the cache memory is in No-Fill Cache mode, then the first logic unit operates, but the write back address allocation becomes disordered making the cache unusable
Solution Approach 1:
The patent applies preliminary action by performing cache memory initialization and setting proper write back address allocation before enabling Hyper-Threading mode. This ensures the cache is in a usable state before the second logic unit attempts to access it, preventing the deadlock.
Solution Approach 2:
The patent changes the cache memory mode parameter from No-Fill Cache to Fill Cache mode by re-initializing the processor in Hyper-Threading enabled mode. This parameter change restores proper write back address allocation and makes the cache usable for the second logic unit.
3Productivity
If BIOS codes are executed from ROM, then system initialization can proceed, but the execution speed is limited compared to cache memory
Solution Approach 1:
The patent applies copying by copying BIOS codes from ROM into the cache memory before execution. This allows the processor to execute BIOS codes from the faster cache memory rather than directly from ROM, significantly improving initialization speed while maintaining the same functional outcome.
Solution Approach 2:
The patent performs the copying of BIOS codes into cache memory as a preliminary action before execution. This preliminary copying step enables the subsequent fast execution phase, resolving the contradiction between execution speed and system complexity.
Data Source
AI summary
A power-on method for a computer system comprising a processor supporting Hyper-Threading, a Read Only Memory (ROM) and a main memory, wherein the processor comprises a cache memory and the ROM comprises BIOS codes. The power-on method comprises the following steps. First, the processor is initialized in a Hyper-Threading disabled mode. The BIOS codes is then copied from the ROM to the cache memory, and the main memory is initialized by executing the BIOS codes therein. Thereafter, the processor is re-initialized in a Hyper-Threading enabled mode after the main memory is initialized. The processor comprises a first logic unit and a second logic unit. When initializing the processor, a first potential is applied to pin A31 of the processor, and a reset signal is delivered to the processor while the pin A31 is at the first potential, such that the processor is initialized in the Hyper-Threading disabled mode.