Hyperabrupt Junction JFET for CMOS Power Amplification
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Solution Overview
Problem
Integration of power amplifiers into standard CMOS technology is costly due to the need for additional processing steps and dedicated substrates, such as GaAs or SiGe BiCMOS technologies, which are not compatible with silicon-based CMOS technologies.
Innovation Solution
A junction field effect transistor (JFET) with a hyperabrupt junction layer is developed, allowing power amplification using standard CMOS processing steps with minimal incremental cost, where the hyperabrupt junction layer is formed by overlapping dopant profiles of opposite types, and the body is doped with the same conductivity type as the gate, enabling high input impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power amplifiers are built using GaAs technologies, then power amplification performance is improved, but manufacturing cost and device complexity increase due to dedicated substrates and processing steps
Solution Approach 1:
The patent merges the JFET structure with standard CMOS processing by forming the JFET device within the same semiconductor substrate using compatible fabrication steps. The source, drain, gate, and hyperabrupt junction are all formed using standard CMOS doping and deposition techniques, eliminating the need for separate GaAs substrates and dedicated processing lines while maintaining power amplification capability
Solution Approach 2:
The invention makes the standard CMOS substrate universal for both digital logic and power amplification applications. By designing the JFET to be formed using the same processing steps as CMOS devices (ion implantation, thermal diffusion, metal deposition), a single substrate can serve multiple functions without requiring specialized materials or processes
2Power
If power amplifiers are built using modified SiGe BiCMOS technologies, then power amplification capability is improved, but manufacturing cost increases due to additional processing steps
Solution Approach 1:
The JFET structure serves itself by utilizing the standard CMOS processing steps to create all necessary components. The hyperabrupt junction is formed using the same ion implantation and thermal processing that create CMOS devices, and the source/drain regions are formed using standard self-aligned techniques, allowing the device to be manufactured without external specialized processes
3Ease of manufacture
If standard CMOS technologies are used for power amplifiers, then manufacturing cost is reduced, but power amplification capability is insufficient without additional processing steps
Solution Approach 1:
The patent achieves power amplification by changing the doping parameters within standard CMOS processes. The hyperabrupt junction is created by controlling dopant concentration gradients through ion implantation and thermal diffusion, achieving the necessary electrical characteristics for power handling while remaining within standard CMOS parameter ranges
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The JFET with a hyperabrupt junction layer provides power amplification compatible with standard CMOS technology, reducing manufacturing costs and processing steps, while maintaining high input impedance and efficient current handling.
Implementation Method 1
The hyperabrupt junction layer (54) is formed by two overlapping dopant profiles of opposite types such that a first dopant concentration profile (150) has a peak concentration depth at a tail end of a second dopant profile (144)
Implementation Method 2
forming a hyperabrupt junction of at least one hyperabrupt junction diode varactor during the same processing step as the formation of thehyperabrupt junction layer
Implementation Method 3
the body of the transistor and the gate of the transistor form a reverse-biased pn junction with depletion regions both in the gate and in the body
Data Source
AI summary
A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.