Hyperboloid Interconnect Profile for Uniform Low-Resistance Wiring
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Solution Overview
Problem
As microelectronic fabrication advances, achieving higher device density through smaller interconnect dimensions and reduced pitch leads to increased resistance, signal delays, and uniformity issues due to high aspect ratios in trenches and vias, causing line wiggling and variations in critical dimensions.
Innovation Solution
The semiconductor device features an interconnect system with multiple portions, including a bottom and top interconnect section, each formed with tapered sidewalls and specific dielectric layers, allowing for a uniform profile and reduced aspect ratios to mitigate line wiggling and metal gapfill errors, achieving a hyperboloid line profile with locally widened critical dimensions for lower line resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnect dimensions are shrunk to increase device density, then device density is improved, but resistance increases and manufacturing precision deteriorates
Solution Approach 1:
The interconnect structure is divided into multiple portions (first, second, third, fourth portions) with different cross-sectional areas arranged vertically. This segmentation allows each portion to be optimized independently, maintaining manufacturability while achieving high device density through the overall compact vertical structure.
Solution Approach 2:
The patent transitions from traditional planar interconnect layouts to a vertical three-dimensional structure. By stacking interconnect portions with varying cross-sectional areas along the vertical dimension, the design achieves high device density without requiring excessive lateral scaling, thereby maintaining manufacturing precision.
2Quantity of substance
If pitch between adjacent components is reduced to increase device density, then device density is improved, but signal delays increase and manufacturing precision deteriorates
Solution Approach 1:
The patent utilizes vertical stacking to reduce lateral pitch between components. By arranging interconnect portions with decreasing cross-sectional areas from bottom to top, the design achieves compact spacing without excessive lateral compression, maintaining signal integrity while increasing device density.
Solution Approach 2:
Different portions of the interconnect structure have different cross-sectional areas optimized for their specific functions. Lower portions with larger areas handle higher current loads, while upper portions with smaller areas reduce capacitance and signal delay, collectively improving reliability while maintaining high density.
3Quantity of substance
If aspect ratio of trenches and vias is increased to achieve smaller dimensions, then device density is improved, but manufacturing precision deteriorates due to line wiggling
Solution Approach 1:
The high aspect ratio structure is segmented into multiple discrete interconnect portions with different cross-sectional areas. This segmentation breaks down a single difficult-to-manufacture high aspect ratio trench into several lower aspect ratio sections, each more amenable to precise fabrication while collectively achieving high device density.
Solution Approach 2:
The interconnect portions feature curved or tapered sidewalls rather than straight vertical profiles. This curvature optimizes the distribution of stress during fabrication and improves metal fill uniformity, reducing line wiggling and enhancing critical dimension control in high aspect ratio structures.
Data Source
AI summary
According to the embodiment of the present invention, a semiconductor device includes an interconnect. The interconnect includes a bottom interconnect section and a top interconnect section. The bottom interconnect section includes a first orientation along a Y-axis. The top interconnect section is coupled to the bottom interconnect section and includes a second orientation along to the Y-axis. The second orientation of the top interconnect section is a vertical reflection of the first orientation of the bottom interconnect section.