3D Hyperchip Stacking for Dense Die-to-Die Interconnects
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Solution Overview
Problem
Traditional integrated circuit packaging techniques face challenges in maximizing die-to-die connections, leading to complex layouts and reduced manufacturing yield due to the use of 2.5D solutions with silicon interposers and through silicon vias (TSVs).
Innovation Solution
The development of hyperchip structures and methods that utilize an active interposer integrated circuit die connected to multiple other dies in a three-dimensional stacked arrangement, enabling heterogeneous integration of various circuit functions with optimized process technology for each die, and employing through silicon vias (TSVs) for high-density and efficient electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2.5D packaging with silicon interposer and TSVs is used to maximize die-to-die connections, then connection density is improved, but layout complexity increases and manufacturing yield decreases
Solution Approach 1:
The patent transitions from 2.5D packaging to true 3D stacking by vertically stacking multiple active interposer dies with device sides facing each other. This dimensional change enables direct face-to-face bonding between dies, eliminating the need for complex lateral routing through a silicon interposer and reducing layout complexity while maintaining high connection density.
Solution Approach 2:
The system is divided into multiple independent active interposer dies, each capable of performing different functions (CPU, GPU, memory, etc.). Each die can be independently fabricated, tested, and replaced, simplifying the overall system architecture and improving manufacturing yield compared to a monolithic interposer approach.
2Quantity of substance
If traditional 2.5D packaging with silicon interposer and TSVs is used to maximize die-to-die connections, then connection density is improved, but manufacturing yield decreases
Solution Approach 1:
By segmenting the system into multiple independent active interposer dies, each die can be manufactured separately with optimized processes for its specific function. This segmentation allows for better defect isolation and higher individual die yields, which translates to higher overall system yield compared to traditional interposer approaches where defects propagate across the entire structure.
Solution Approach 2:
The patent changes the manufacturing parameters by using standard active interposer die fabrication processes rather than specialized interposer manufacturing. This allows leveraging existing high-yield semiconductor manufacturing capabilities while achieving the desired connection density through 3D stacking architecture.
3Volume of moving object
If active interposer dies are stacked in three-dimensional arrangement with device sides facing each other, then form factor is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent achieves compact form factor by stacking active interposer dies vertically in the Z-dimension rather than spreading them out laterally in the X-Y plane. This 3D arrangement reduces the footprint while maintaining all necessary connections through direct face-to-face bonding interfaces between stacked dies.
Solution Approach 2:
Each active interposer die is designed as a universal building block that can serve multiple functions (processing, memory, I/O) depending on its configuration. This universality simplifies manufacturing by using standardized die designs and bonding processes that can be applied repeatedly across different product configurations, reducing overall manufacturing complexity despite the 3D stacking architecture.
Data Source
AI summary
Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.