3D Hyperchip Stacking With Active Interposer Die Connections
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Solution Overview
Problem
Modern integrated circuit packaging techniques face challenges in maximizing die-to-die connections while maintaining a minimal footprint, leading to complex layouts and depressed yield rates.
Innovation Solution
The use of an active interposer die with through silicon vias (TSVs) and microbumps for face-to-face connections between integrated circuit chips, allowing for high-density, heterogeneous integration of various functionalities in a smaller form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2.5D packaging with silicon interposer and TSVs is used to maximize die-to-die connections, then connection density and speed are improved, but layout complexity and manufacturing complexity increase leading to depressed yield rates
Solution Approach 1:
The patent transitions from planar 2.5D interconnection to three-dimensional vertical stacking, where multiple dies are stacked in the Z-direction and connected via TSVs. This dimensional change allows high connection density without increasing lateral footprint or layout complexity, as connections are established through vertical pathways rather than complex planar routing.
Solution Approach 2:
The patent introduces an active interposer die as an intermediary component that facilitates heterogeneous integration between different die types (e.g., logic die, memory die, graphics die). The interposer provides standardized TSV and microbump interfaces that simplify the connection process between diverse dies, reducing manufacturing complexity while enabling high connection density.
2Quantity of substance
If more die-to-die connections are implemented in traditional packaging, then integration density is improved, but manufacturing yield decreases due to complex layouts
Solution Approach 1:
By moving to 3D stacking architecture, the patent achieves high integration density through vertical arrangement of dies rather than lateral expansion. This dimensional shift simplifies the manufacturing process by using standardized TSV formation and microbump attachment procedures, thereby maintaining or improving yield rates while increasing integration density.
Solution Approach 2:
The patent employs preliminary wafer-level processing steps including TSV formation, die attachment, and interconnection establishment before final packaging. These preliminary actions are performed on wafers in bulk rather than on individual chips, enabling economies of scale and consistent quality control that improve manufacturing yield while achieving high integration density.
3Adaptability or versatility
If heterogeneous integration of diverse functionalities is achieved, then system functionality is improved, but process complexity increases
Solution Approach 1:
The active interposer die serves as a universal mediator that provides standardized interfaces for connecting heterogeneous dies with different functionalities (logic, memory, graphics, etc.). The interposer's standardized TSV and microbump patterns simplify the integration process by providing consistent connection protocols across different die types, reducing process complexity while enabling diverse system functionality.
Solution Approach 2:
The patent designs the interposer with universal, multi-functional capabilities that can accommodate various die types and connection configurations. The standardized interposer structure with configurable TSV and microbump arrangements provides a universal platform for heterogeneous integration, allowing the same basic architecture to support multiple functionality combinations without increasing process complexity.
Data Source
AI summary
Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.