3D Hyperchip Stacking for High-Density Die Interconnects
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Solution Overview
Problem
Modern integrated circuit packaging techniques face challenges in maximizing die-to-die connections, leading to complex layouts and depressed yield rates due to the use of traditional 2.5D solutions with silicon interposers and through silicon vias (TSVs).
Innovation Solution
The implementation of a hyperchip structure with an active interposer die that enables three-dimensional stacked arrangements, allowing for heterogeneous integration of multiple circuit functions such as CPUs, graphics, modems, and memory, using TSVs for high-density connections and optimized process technology for each function, while enabling a smaller form factor and reconfiguration capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2.5D solutions with silicon interposers and through silicon vias are used to maximize die-to-die connections, then connection density and speed are improved, but layout complexity increases and manufacturing yield decreases
Solution Approach 1:
The patent transitions from 2.5D interposer-based connections to true 3D stacked die architecture, where multiple dies are vertically stacked and interconnected through through-die vias. This dimensional change eliminates the need for lateral routing through an interposer, thereby reducing layout complexity while maintaining high connection density through vertical stacking.
Solution Approach 2:
The patent extracts and eliminates the silicon interposer component from the traditional 2.5D architecture. By directly stacking dies and forming interconnections through the dies themselves, the interposer is removed, simplifying the overall structure and reducing manufacturing complexity while achieving comparable or superior connection density.
2Quantity of substance
If traditional 2.5D solutions with silicon interposers and through silicon vias are used to maximize die-to-die connections, then connection density is improved, but manufacturing yield rate decreases
Solution Approach 1:
By adopting 3D stacked architecture with through-die vias, the patent enables more direct and controllable interconnection paths compared to 2.5D lateral routing. This dimensional change simplifies the manufacturing process by eliminating complex interposer integration steps, thereby improving manufacturing yield while maintaining high connection density.
Solution Approach 2:
The patent performs preliminary formation of through-die vias and interconnect structures within each die before stacking. This preliminary action allows for better control and quality assurance of critical interconnection features, improving manufacturing yield by preventing defects that would arise from post-assembly interconnection processes in traditional 2.5D approaches.
3Area of stationary object
If three-dimensional stacked arrangements with active interposer die are implemented, then footprint is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes vertical stacking in the third dimension to achieve high integration density within a small footprint. By moving connections from lateral (2D) to vertical (3D) space, the system achieves compact form factor while the modular nature of stacked dies actually simplifies manufacturing compared to planar integration.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate dies that are stacked vertically. Each die can be manufactured independently using standard CMOS processes, and then assembled through precise alignment and bonding. This segmentation allows for specialized optimization of each die layer while simplifying the overall manufacturing process compared to monolithic integration.
4Reliability
If heterogeneous integration of multiple circuit functions is performed using optimized process technology for each function, then circuit performance is improved, but integration complexity increases
Solution Approach 1:
The patent applies different process technologies and materials to specific die layers based on their functional requirements. For example, logic dies may use advanced CMOS nodes while memory dies use optimized SRAM processes. This local quality approach allows each component to be optimized for its specific function, improving overall circuit performance while the modular stacked architecture manages integration complexity through standardized interconnection interfaces.
Data Source
AI summary
Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.