Hyperchip Face-to-Face Die Stacking With TSV Interposer Routing
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Solution Overview
Problem
Modern integrated circuit packaging techniques face challenges in maximizing die-to-die connections while maintaining a minimal footprint, leading to complex layouts and depressed yield rates.
Innovation Solution
The use of an active interposer die with through silicon vias (TSVs) and microbumps for face-to-face connections between integrated circuit chips, allowing for high-density, heterogeneous integration of various functionalities in a smaller form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2.5D packaging with silicon interposer and TSVs is used to maximize die-to-die connections, then connection density and speed are improved, but layout complexity increases and manufacturing yield decreases
Solution Approach 1:
The invention divides the interconnection function into two separate components: a passive interposer substrate that provides the physical interconnection structure, and an active controller chip that handles signal processing. This segmentation allows the interposer to be optimized purely for connectivity without the complexity of active circuit design, while the controller chip can be optimized for signal processing. The passive interposer uses simple TSVs and trace routing without requiring complex active circuit layouts.
Solution Approach 2:
The passive interposer substrate acts as an intermediary between multiple controller chips, providing a standardized interface and physical mounting structure. It mediates the connections between chips without requiring complex direct chip-to-chip routing, simplifying the overall system layout. The interposer's TSVs and trace layers serve as intermediate connection paths that reduce the complexity of direct inter-chip routing.
2Quantity of substance
If traditional 2.5D packaging with silicon interposer and TSVs is used to maximize die-to-die connections, then connection density is improved, but manufacturing yield decreases
Solution Approach 1:
By separating the passive interposer fabrication from the active controller chip fabrication, each component can be manufactured independently using optimized processes. The passive interposer can be fabricated with standard TSV and trace routing processes that are well-established and have high yield, while the controller chips can be manufactured using advanced semiconductor processes in separate fabrication lines. This segmentation eliminates the need for complex co-fabrication processes that would depress yield.
Solution Approach 2:
The invention changes the functional parameters of the interposer from active to passive, which fundamentally alters the manufacturing requirements. A passive interposer does not require complex active circuit fabrication, photolithography for circuit patterns, or delicate active component integration. Instead, it uses simpler processes like TSV formation, dielectric deposition, and trace routing, all of which have higher manufacturing yields and are more robust to process variations.
3Adaptability or versatility
If an active interposer is used to provide routing and signal processing, then functionality is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The invention segments the system into a passive interposer that handles only physical interconnection and an active controller chip that provides routing and signal processing. This segmentation eliminates the need for an active interposer, as the signal processing functions are moved to the controller chip where they can be implemented using standard semiconductor fabrication processes. The passive interposer remains simple in structure, providing only the mechanical and electrical interconnection framework.
Solution Approach 2:
The active signal processing functionality is extracted from the interposer and placed in the controller chip. This extraction allows the interposer to remain passive and simple, while the controller chip assumes the burden of complex routing and signal processing logic. The controller chip can be programmed or configured to provide the necessary routing functions, eliminating the need for hardwired complex circuits in the interposer.
Data Source
AI summary
Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.