Hyperdimensional Mixed-Signal Processor Architecture
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Solution Overview
Problem
Current hyperdimensional computing (HDC) hardware systems face challenges in reducing power and area consumption for classification and inference tasks, as they rely on digital circuitries that are inefficient in terms of power and area usage.
Innovation Solution
A mixed-signal architecture with locally connected 1-bit processing units and multiplexers is introduced, where each processing unit has a local memory and analog circuitry for simplified operations like majority rule and Hamming distance calculations, reducing the need for global memory and digital circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If digital circuitries are used to perform majority rule and Hamming distance calculation, then computation accuracy is maintained, but power consumption and area usage increase
Solution Approach 1:
The patent replaces digital circuitry with mixed-signal circuitry that combines digital and analog components. Specifically, it uses analog circuits to perform majority rule and Hamming distance calculations, substituting purely digital mechanical operations with a hybrid approach that reduces power consumption while maintaining computational accuracy through carefully designed analog-digital interfaces
Solution Approach 2:
The patent changes the operational parameters by using 1-bit processing units instead of traditional multi-bit digital units. This parameter change enables the system to perform HDC operations with reduced complexity, lower power consumption, and simplified circuitry while maintaining the necessary computational accuracy through the collective behavior of multiple 1-bit units
2Ease of operation
If global memory is used for HDC operations, then data accessibility is improved, but area consumption and access time increase
Solution Approach 1:
The patent segments the global memory into local memory units distributed across multiple processing units. Each processing unit has its own local memory, dividing the monolithic global memory structure into smaller, distributed segments that reduce access time and area consumption while maintaining data accessibility through local processing
Solution Approach 2:
The patent transitions from a centralized global memory architecture to a distributed memory architecture across multiple processing units. This dimensional change in memory organization allows parallel access to different data segments, reducing access time and enabling simultaneous operations without contending for a single global memory resource
3Adaptability or versatility
If fully digital architecture is used, then operational flexibility is maintained, but power consumption and area usage increase
Solution Approach 1:
The patent substitutes fully digital circuitry with mixed-signal circuitry that uses analog components for specific HDC operations. This substitution reduces area consumption by leveraging the compact nature of analog circuits for tasks like majority rule and Hamming distance calculation, while digital components maintain operational flexibility for control and data processing
Solution Approach 2:
The patent creates multi-functional processing units that can perform both digital operations and analog HDC operations within the same hardware structure. This universality allows the system to maintain operational flexibility for different computational tasks while reducing overall area consumption by avoiding separate dedicated circuits for each operation type
Data Source
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AI summary
A device for hyperdimensional computing comprising: an array of m x n 1-bit processing units; each processing unit comprising a 1-bit logic unit and a memory unit; at least one input terminal for receiving an input hypervector; n 1-bit multiplexers for selecting: the input of a processing unit in the first row, the input of a processing unit of the last row or the input of the at least one input terminal; wherein the array is arranged such that each processing unit is connected to its four nearest neighboring processing units, where: one neighboring processing unit for each processing unit of the first row of the array is the processing unit of the last row sharing the same column of the array; one neighboring processing unit for each processing unit of the last column of the array is the processing unit of the first column and next row; one neighboring processing unit for the processing unit at position m x n is the processing unit at position 1×1. Also, methods for manufacturing and using the device.