Multi-Node Memory Coherency via Hyperervisor Packet Routing

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Solution Overview

Problem

In virtual computer systems, the wait time for memory page data between network nodes introduces latency and reduces performance due to the need for data transfer between nodes when memory pages are not mapped to the receiving node.

Innovation Solution

Implementing a system where data packets are transmitted directly to the node with mapped memory pages, eliminating the need for inter-node data transfer by distributing the operating system across multiple network nodes and using network interface controllers to determine memory mapping and facilitate packet transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the first network node waits for memory page data from the second network node, then memory coherency is maintained, but performance and processing speed are reduced

Engineering Contradiction:
Improvememory coherencyVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by having the second network node prepare memory page data in advance and make it available before the first network node needs it. The hyperervisor proactively manages memory page mappings and pre-positions data across network nodes, eliminating the need for the first node to wait idle for memory page data.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The hyperervisor acts as an intermediary between network nodes, managing memory page mappings and coordinating data transfer. It receives interrupts from network nodes, determines appropriate memory page mappings, and facilitates efficient data transfer by routing packets to nodes with available memory pages, thus maintaining coherency without direct waiting between nodes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data packets are transferred between network nodes, then memory coherency is maintained, but latency increases

Engineering Contradiction:
Improvememory coherencyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-establishing memory page mappings across network nodes before data packets arrive. The hyperervisor proactively manages these mappings and pre-positions data, so when a packet arrives at a node without the required memory page, the data is already available or can be rapidly transferred without significant latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where network nodes send interrupts to the hyperervisor when they need memory page data. The hyperervisor responds by determining appropriate memory page mappings and facilitating data transfer. This feedback loop enables dynamic adaptation to memory coherency requirements while minimizing latency through efficient routing decisions.

Inventive Principle:
Principle #23Feedback

3Reliability

If the operating system is distributed across multiple network nodes, then system availability is improved, but device complexity increases

Engineering Contradiction:
Improvesystem availabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The operating system is segmented and distributed across multiple network nodes, with each node hosting portions of the OS and associated virtual machines. This segmentation improves system availability by allowing the system to continue operating even if individual nodes fail, while the hyperervisor coordinates the distributed components to manage complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The hyperervisor serves multiple functions: it manages memory page mappings, routes data packets between nodes, handles interrupts from network nodes, and coordinates OS operations across the distributed system. This multi-functionality consolidates control logic into a single coordinating component, reducing overall system complexity despite the distributed architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10819783B1Managing a data packet for an operating system associated with a multi-node system
Publication Date: 2020.10.27 AMPERE COMPUTING LLC
  • US10819783B1 patent drawing
  • US10819783B1 patent drawing
  • US10819783B1 patent drawing

AI summary

Various aspects provide for managing memory in virtual computer system. For example, a system can include a first network node and a second network node. The first network node receives a data packet via a first hardware network controller. The first network node also transmits the data packet over a communication channel via a second hardware network controller in response to a determination that memory data for the data packet is not mapped to the first network node. The second network node receives the data packet via the communication channel and provides the data packet to an operating system associated with the first network node and the second network node.