Hypergraph Hardware Accelerator with Priority Caching
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Solution Overview
Problem
Existing hypergraph processing systems face performance limitations due to poor data locality, leading to inefficient memory access and increased energy overheads.
Innovation Solution
A data-centric hardware accelerator for hypergraph processing is developed, featuring a data loader, address translator, task trigger, processor, and reducer. This accelerator employs a load-trigger-reduce execution model, prioritizes data based on reusability, and utilizes a priority-based multi-level caching mechanism to maximize data locality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple scheduling strategy is used for hypergraph processing, then device complexity is reduced, but memory access performance deteriorates due to low cache hit rates
Solution Approach 1:
The patent applies preliminary action by pre-loading hypergraph data into on-chip caches before processing begins. The data loader module loads vertex data, hyperedge data, and attribute data into respective cache memories in advance, ensuring that frequently accessed data is already available in high-speed memory when processing tasks are executed, thereby improving cache hit rates without complicating the scheduling strategy
Solution Approach 2:
The patent segments the hypergraph data into distinct components stored in separate cache regions: vertex data in vertex cache,hyperedge data inhyperedge cache, and attribute data in attribute cache. This segmentation allows the simple scheduling strategy to efficiently manage access to specific data types without requiring complex global scheduling, while still achieving high memory access performance through localized cache hits
2Productivity
If buffer memory is added to improve data locality, then data reuse is enhanced, but energy overhead increases significantly
Solution Approach 1:
The patent applies local quality by providing dedicated cache memory for each data type (vertex cache,hyperedge cache,attribute cache) rather than using a single general-purpose buffer. Each cache is optimized for its specific data type and accessed by relevant processing units, maximizing data reuse efficiency while minimizing the energy overhead associated with managing and accessing a single large buffer memory structure
3Device complexity
If off-chip memory is used for hypergraph data storage, then device complexity is reduced, but memory access performance deteriorates due to poor data locality
Solution Approach 1:
The patent applies the nested doll principle by creating a hierarchical memory structure where small on-chip caches (vertex cache,hyperedge cache,attribute cache) are nested within the larger off-chip memory system. Frequently accessed hypergraph data is nested in the fast on-chip caches, while less frequently accessed data remains in off-chip memory, achieving high processing performance for active data without the complexity of a fully on-chip memory system
Data Source
AI summary
The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermediate results. In view of the shortcomings of task-centric hardware accelerators, the present invention can prevent any possible data conflict during parallel execution of multiple processing units.