Hypergraph-Based Spare Cell Placement for IC Logic Cones
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Solution Overview
Problem
Existing methods for placing spare cell locations in integrated circuit designs are inefficient, often resulting in irregular distribution and insufficient spare cells near critical logic, leading to challenges in implementing engineering change orders (ECOs) without violating design requirements or requiring extensive computational iterations.
Innovation Solution
A method that identifies overlapping candidate spare cell regions associated with logic cones, assigns different spare cell insertion rates, and uses a hypergraph to determine the optimal placement of spare cells, ensuring they are proximate to critical logic and minimizing the number needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If filler cells are randomly placed throughout the layout with a global filler percentage, then the implementation of ECOs is simplified, but the distribution becomes irregular and critical logic areas do not receive enough spare cells
Solution Approach 1:
The patent applies local quality by assigning different filler percentages to different logic cones based on their stability characteristics. Unstable logic cones receive higher filler percentages (e.g., 10-20%) while stable logic cones receive lower percentages (e.g., 0-5%). This localized differentiation ensures that spare cells are concentrated where they are most needed near critical logic, rather than distributing them uniformly across the entire design.
Solution Approach 2:
The patent segments the circuit design into multiple logic cones and processes each cone independently for filler cell placement. By dividing the global placement problem into localized cone-level problems, the method can optimize spare cell distribution for each logical region separately, ensuring that unstable areas receive adequate coverage while avoiding over-provisioning in stable areas.
2Stability of the object's composition
If placement tools push filler cells away from critical logic to maintain stability, then layout stability is improved, but spare cells are not located close enough to be useful for ECOs
Solution Approach 1:
The patent resolves this contradiction by applying different stability constraints to different logic cones. Unstable logic cones are identified and assigned higher filler percentages, allowing spare cells to be placed within or near these cones despite potential layout perturbations. Stable logic cones maintain lower filler percentages and stricter placement constraints, preserving layout stability where it is already achieved. This localized approach ensures spare cells are positioned close to critical logic in unstable areas without compromising overall design stability.
3Reliability
If a high filler percentage is applied globally to ensure enough spare cells, then spare cell availability increases, but the number of required cells increases and stable areas receive too many filler cells
Solution Approach 1:
The patent optimizes the total filler cell count by applying localized filler percentages based on logic cone stability. Unstable logic cones receive higher filler percentages (10-20%) where spare cells are critically needed, while stable logic cones receive lower percentages (0-5%). This targeted approach ensures adequate spare cell availability in critical areas without unnecessarily increasing the total filler cell count across the entire design, reducing area overhead and resource waste.
4Productivity
If placement tools use quadratic placement to minimize wire length, then routing efficiency is improved, but logic clustering occurs which reduces spare cell effectiveness
Solution Approach 1:
The patent addresses the logic clustering issue by applying different placement strategies to different logic cones. In unstable logic cones where spare cell accessibility is critical, the method allows for greater placement flexibility and accepts some wire length increase to ensure spare cells are positioned near critical logic. In stable logic cones, quadratic placement can be applied more aggressively to minimize wire length. This localized differentiation maintains routing efficiency overall while ensuring spare cell effectiveness in critical regions.
Data Source
AI summary
Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.