HyperJTAG System Multiplexing Debug Signals for Multi-Core SoCs
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Solution Overview
Problem
Current debug systems for System-on-a-Chip (SoC) devices with multiple processor cores face challenges in interfacing and debugging due to limited pins, inaccessibility of control and bus signals, and the inability to simultaneously access multiple processor cores using traditional JTAG protocols and instruments.
Innovation Solution
The HyperJTAG system, which includes a probe and on-chip instrumentation with concentrator and de-concentrator mechanisms, allows multiple test instruments to simultaneously interface with multiple processor cores by multiplexing and demultiplexing signals, enabling independent control and access to each core without the need for dedicated pins or custom configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional JTAG protocol is used to interface with processor cores, then each core requires dedicated access, but the number of pins and device complexity increases
Solution Approach 1:
Multiple JTAG interfaces are merged into a single shared physical interface. The patent implements a time-division multiplexed JTAG interface where multiple processor cores share common TCK, TMS, TDI, and TDO pins through sequential access control, eliminating the need for separate pin sets for each core.
Solution Approach 2:
A single JTAG interface structure is designed to serve multiple functions by accommodating multiple processor cores. The interface can be dynamically configured to access different cores through software control and state machine management, making the interface universal rather than dedicated to a single core.
2Reliability
If traditional ICE connects to numerous device pins including address, data, and control signals, then debugging capability is enhanced, but pin availability and ease of manufacture deteriorate
Solution Approach 1:
The essential debugging functionality is extracted from the complex traditional ICE architecture. Instead of requiring numerous pins for address, data, and control signals, the patent extracts only the critical JTAG control signals (TCK, TMS, TDI, TDO) needed for debugging, eliminating the need for extensive pin connections while maintaining core debugging capabilities.
Solution Approach 2:
A boundary scan register and state machine act as intermediaries between the minimal JTAG interface and the processor cores. This intermediary structure enables full debugging control through a reduced pin set by providing signal regulation, state management, and core selection functions that would otherwise require numerous direct connections.
3Productivity
If multiple debug probes are used to access multiple processor cores, then simultaneous debugging is enabled, but connector sharing and device complexity increase
Solution Approach 1:
The JTAG interface maintains continuous operational capability across multiple cores through time-division multiplexing. Rather than requiring separate physical interfaces for simultaneous access, the system provides continuous debugging functionality by rapidly switching between cores in a time-division manner, creating the effect of simultaneous access through high-speed sequential operation.
4Adaptability or versatility
If standardized JTAG protocol is used, then compatibility with off-the-shelf probes is improved, but ability to wait for access and handle multiple cores simultaneously deteriorates
Solution Approach 1:
The JTAG interface transitions from a static single-core protocol to a dynamic multi-core system. The state machine and control logic are designed to dynamically allocate access to different processor cores based on operational needs, enabling the interface to adapt its behavior in real-time while maintaining standard JTAG signal compatibility.
Data Source
AI summary
A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism. The probe de-concentrator de-concentrates the second serial signal stream into signals to be directed to at least one of the testing instruments. Using this system, the testing instruments are able to simultaneously access and control respective processor cores. In one preferred embodiment the plurality of signals are directed to the processor cores using a plurality of loops, each loop having a chain of nodes, each of the processor cores connected to a respective node.